TrustZone的监控模式和IFAR,IFSR,DFAR,DFSR [英] TrustZone monitor mode and IFAR, IFSR, DFAR, DFSR
问题描述
在ARM的的TrustZone监控模式就能够在监控模式中止。监控模式总是执行在安全的世界或上下文。我们怎样才能知道是什么地址和原因引起了正常的世界发生故障时,陷阱监控模式的指令中止的和的数据故障的载体?
The ARM TrustZone monitor mode can trap aborts in monitor mode. The monitor mode always executes in the secure world or context. How can we know what address and reason caused a fault in the normal world when it traps to the monitor mode instruction abort and data fault vectors?
IFSR
,的 IFAR
,的 DFSR
和的 DFAR
被存入银行 CP15 的寄存器。
推荐答案
值得注意的是,只有外部中止可以配置监视模式进行拍摄,因此MMU访问故障不会被困住了。
It is worth noting that only external aborts can be configured to be taken in monitor mode, so MMU access faults will not be trapped.
对于主要的问题:所有的安全/非安全库存的状态寄存器的而在监控模式的是由CP15安全配置寄存器中的NS位的状态来控制:当它被设置,您访问非安全版本,当它是清楚你访问安全的版本。
As for the main question: the state of all Secure/Non-secure banked registers while in monitor mode is controlled by the state of the cp15 Secure Configuration Register NS bit: when it is set, you access Non-secure versions, and when it is clear you access Secure versions.
以下是一些内联 GCC
code,它允许任何的安全的世界的模式,以检查这些 CP15
寄存器。
The following is some inline gcc
code which allows any secure world mode to inspect these CP15
registers.
#define MODE_MONITOR 0x16
unsigned int mode;
unsigned int world;
unsigned int dfar;
unsigned int dfsr;
unsigned int ifar;
unsigned int ifsr;
asm (" mrs %0, cpsr\n" /* Save mode. */
" mrc p15, 0, %1, c1, c1, 0\n"
" orr %1, %1, #1\n" /* Set NS bit in SCR. */
" cpsid aif, %6\n" /* To monitor mode... */
" mcr p15, 0, %1, c1, c1, 0\n"
" mrc p15, 0, %2, c6, c0, 0\n"
" mrc p15, 0, %3, c5, c0, 0\n"
" mrc p15, 0, %4, c6, c0, 2\n"
" mrc p15, 0, %5, c5, c0, 1\n"
" bic %1, %1, #1\n" /* Clear NS bit in SCR. */
" mcr p15, 0, %1, c1, c1, 0\n"
" isb\n"
" msr cpsr, %0\n"
: "=&r" (mode), "=&r" (world),
"=r"(dfar), "=r"(dfsr),
"=r"(ifar), "=r"(ifsr)
: "I" (MODE_MONITOR));
printf("DFAR: %.8x dfsr: %.8x IFAR: %.8x ifsr: %.8x\n",
dfar, dfsr, ifar, ifsr);
这篇关于TrustZone的监控模式和IFAR,IFSR,DFAR,DFSR的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!