你能帮助我理解基于ARM的移动deviec外设寻址和总线结构？ [英] Can you help me understand Peripherals Addressing and Bus architecture in ARM-based mobile deviec?
问题描述
我会先说，我不是在该领域的专家和我的问题可能包含的误解，在这种情况下，如果你纠正我，我会很高兴，并附加资源，让我能学到更多细节。
I will first say that I'm not expert in the field and my question might contain misunderstanding, in which case, I'll be glad if you correct me and attach resources so I can learn further details.
我想弄清楚的方式，系统总线以及如何出现在移动设备中的各种设备（如传感器芯片，支持WiFi / BT系统级芯片，触摸屏等）由CPU处理（和其他MCU）。
I'm trying to figure out the way that the system bus and how the various devices that appear in a mobile device (such as sensors chips, wifi/BT SoC, touch panel, etc.) are addressed by the CPU (and by other MCUs).
在PC世界里，我们有总线仲裁这条路的命令/数据的设备，然后，据我所知，地址是硬连接在电路板（纠正我，如果我错了）。然而，在移动世界我没发现，寻址方式的任何证据;我没有发现，ARM公司标准化高级微控制器总线架构，我不知道，不过，适用于它位于相同的SoC内部的部件（如CPU-核）的标准（即的Exynos，OMAP的Snapdragon等），或者还是否会影响外设接口。特别是我在问什么组件负责分配上的地址，外围设备和MMIO地址？
In the PC world we have the bus arbitrator that route the commands/data to the devices, and, afaik, the addresses are hardwired on the board (correct me if I'm wrong). However, in the mobile world I didn't find any evidence of that type of addressing; I did find that ARM has standardized the Advanced Microcontroller Bus Architecture, I don't know, though, whether that standard applied for the components (cpu-cores) which lies inside the same SoC (that is Exynos, OMAP, Snapdragon etc.) or also influence peripheral interfaces. Specifically I'm asking what component is responsible on allocating addresses to peripheral devices and MMIO addresses?
一个更基本的问题是是否有在移动设备架构，甚至存在总线管理或者有某种明星拓扑结构（其中CPU为中心）。
A more basic question would be whether there even exist a bus management in the mobile device architecture or maybe there is some kind of "star" topology (where the CPU is the center).
从<一个href=\"http://stackoverflow.com/questions/23783649/writing-a-device-driver-for-platform-bus-in-embedded-systems\">this问题我得到的IM pression这些设备被视为的平台设备的，即那些通过总线直接连接到CPU，而不是设备。不过，我的问题是如何在操作系统知道如何来解决呢？然后其他线程，<一个href=\"http://stackoverflow.com/questions/15610570/what-is-the-difference-between-platform-driver-and-normal-device-driver\">this和<一个href=\"http://stackoverflow.com/questions/14972584/how-do-the-files-in-dev-match-linuxs-model-of-a-device\">this有关平台设备/驱动程序让我感到困惑。
From this question I get the impression that these devices are considered as platform devices, i.e., devices that are connected directly to the CPU, and not through a bus. Still, my question is how does the OS knows how to address them? Then other threads, this and this about platform devices/drivers made me confused..
推荐答案
ARM和x86的之间的区别是的 PIO 的。有对ARM无特殊指令访问I / O设备。一切都是通过内存映射I / O完成。
A difference between ARM and the x86 is PIO. There are no special instruction on the ARM to access an I/O device. Everything is done through memory mapped I/O.
一个第二差是ARM（和RISC一般）有一个单独的加载/存储单元（多个）是从正常的逻辑分离。
A second difference is the ARM (and RISC in general) has a separate load/store unit(s) that are separate from normal logic.
第三个区别是，ARM许可证都 架构 和逻辑核心。第一种是像苹果，三星等公司谁做核心的洁净室版本中使用。对于第二组，究竟是谁买的逻辑ARM CPU将包括来自 AMBA 家庭的东西。
A third difference is that ARM licenses both the architecture and logic core. The first is used by companies like Apple, Samsung, etc who make a clean room version of the cores. For the second set, who actually buy the logic the ARM CPU will include something from the AMBA family.
从ARM其它外设，如GIC（的Cortex-A中断控制器），NVIC（Cortex-M的中断控制器），L2控制器，UART接口等将全部配备了AMBA接口类型。第三方公司（Chipidea的USB等），也可能使逻辑，设置为特定的ARM总线。
Other peripherals from ARM such as a GIC (Cortex-A interrupt controller), NVIC (Cortex-M interrupt controller), L2 controllers, UARTs, etc will all come with an AMBA type interface. 3rd party companies (ChipIdea USB, etc) may also make logic that is setup for a specific ARM bus.
请注意在Wikipedia文件AMBA几个公共汽车类型。
Note AMBA at Wikipedia documents several bus types.
- 建业 - 一个较低的速度外设总线;有点像的南桥的
- AHB - 好几个版本（较老的北桥的）
- AXI - 一个新的多CPU（主）高速总线。例如 NIC301 。
- ACE - 一个AXI扩展
- APB - a lower speed peripheral bus; sort of like south bridge.
- AHB - several versions (older north bridge).
- AXI - a newer multi-CPU (master) high speed bus. Example NIC301.
- ACE - an AXI extension.
一个单独的CPU /核心可具有一个，两个，或多个主连接到一个AXI总线。连接到AXI总线可能有多个内核。在加载/存储的和的取指令的核心可以用多个端口派遣请求分离奴隶单位。该SOC厂商将平衡预计内存带宽需求的端口数量。图形处理器也经常连接到AXI总线与DDR奴隶一起。
A single CPU/core may have one, two, or more master connection to an AXI bus. There maybe multiple cores attached to the AXI bus. The load/store and instruction fetch units of a core can use the multiple ports to dispatch requests to separate slaves. The SOC vendor will balance the number of ports with expected memory bandwidth needs. GPUs are also often connected to the AXI BUS along with DDR slaves.
这是事实，没有100％的标准拓扑;尤其是当你考虑所有可能的未来ARM的设计。然而，典型的拓扑结构包括一个顶级的 AXI 一些 AHB 连接的外围设备。一个或多个二级建业（公交车）将提供访问低速外设。不是每个SOC厂商愿意花时间重新设计的外设与老AHB接口速度可能相当精细的设备。
It is true that there is no 100% standard topology; especially if you consider all possible future ARM designs. However, typical topologies will include a top level AXI with some AHB peripherals attached. One or multiple 2nd level APB (buses) will provide access to low speed peripherals. Not every SOC vendor wants to spend time to redesign peripherals and the older AHB interface speeds maybe quite fine for a device.
您的问题被标记的嵌入式Linux的的。在大多数情况下的Linux只需知道的物理地址。有时，外围总线控制器可能需要配置。例如，一个APB可能被配置为允许或禁止用户模式。此配置可以在启动时被锁定。通常情况下，Linux没有太在意，直接总线结构。程序员可能有$ C $光盘结构的知识驱动（如IRAM是fasters，等等）。
Your question is tagged embedded-linux. For the most part Linux just needs to know the physical addresses. On occasion, the peripheral BUS controllers may need configuration. For instance, an APB may be configure to allow or disallow user mode. This configuration could be locked at boot time. Generally, Linux doesn't care too much about the bus structure directly. Programmers may have coded a driver with knowledge of the structure (like IRAM is fasters, etc).
不过，我的问题是如何在操作系统知道如何来解决呢？
Still, my question is how does the OS knows how to address them?
旧的Linux内核把这些定义中的机文件的并通过了的平台的资源结构，包括中断号和寄存器组的物理地址。在较新的Linux版本，这个信息是包含在的开放固件或设备树的文件。
Older Linux kernels put these definitions in a machine file and passed a platform resource structure including interrupt number, and the physical address of a register bank. In newer Linux versions, this information is included with Open Firmware or device tree files.
具体来说，我问什么组件负责分配上的地址，外围设备和MMIO地址？
Specifically I'm asking what component is responsible on allocating addresses to peripheral devices and MMIO addresses?
的物理地址由SOC的制造商设置。 Linux的的平台支持的将使用MMU把它们映射为不可缓存的一些未使用的范围。通常情况下，物理地址可能是非常的的备用的这样的虚拟重映包更密集。每招一个TLB命中（MMU缓存）。
The physical addresses are set by the SOC manufacturer. Linux platform support will use the MMU to map them as non-cacheable to some un-used range. Often the physical addresses may be very spare so the virtual remapping pack more densely. Each one incurs a TLB hit (MMU cache).
下面是一个使用AXI与样本SOC总线结构的Cortex-M和Cortex-A连接。
Here is a sample SOC bus structure using AXI with a Cortex-M and Cortex-A connected.
的PBRIDGE组件APB桥，它被连接在一个星形拓扑。正如其他建议，你需要寻找一个特定的SOC文档细节。但是，如果你没有SOC，并试图大致了解ARM，一些信息上面会帮你，不管你有什么SOC。
The PBRIDGE components are APB bridges and it is connected in a star topology. As others suggests, you need to look a your particular SOC documentation for specifics. However, if you have no SOC and are trying to understand ARM generally, some of the information above will help you, no matter what SOC you have.
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