在ARM原子操作 [英] Atomic operations in ARM

问题描述

我已经工作了ARM的嵌入式操作系统，但甚至有指ARMARM和Linux源代码后，有几件事情我不明白有关的架构。

I've been working on an embedded OS for ARM, However there are a few things i didn't understand about the architecture even after referring to ARMARM and linux source.

原子操作。

ARM公司表示，加载和保存指令是原子和它的执行是保证中断处理程序执行之前完成。通过查看

ARM ARM says that Load and Store instructions are atomic and it's execution is guaranteed to be complete before interrupt handler executes. Verified by looking at

arch/arm/include/asm/atomic.h :
    #define atomic_read(v)  (*(volatile int *)&(v)->counter)
    #define atomic_set(v,i) (((v)->counter) = (i))

然而，问题就来了的时候，我想操纵原子这个值使用CPU指令（atomic_inc，atomic_dec，atomic_cmpxchg等），它使用LDREX和STREX对ARMv7（我的目标）。

However, the problem comes in when i want to manipulate this value atomically using the cpu instructions (atomic_inc, atomic_dec, atomic_cmpxchg etc..) which use LDREX and STREX for ARMv7 (my target).

ARMARM不说被封锁在本节有关的任何中断，所以我认为在LDREX和STREX之间可能发生中断。它提到的事情是有关锁定内存总线。我想这仅适用于MP系统，其中可以有更多CPU试图在同一时间访问相同的位置很有帮助。但对于UP（也可能是MP），如果定时器中断（或IPI对SMP）的LDREX和STREX这个小窗口火灾，异常处理程序会执行可能改变CPU上下文，并返回到新的任务，然而令人震惊的部分来自于现在，执行CLREX，因此除去previous线程持有任何排它锁。因此，如何利用LDREX和STREX比LDR和STR用于原子更好UP系统上？

ARMARM doesn't say anything about interrupts being blocked in this section so i assume an interrupt can occur in between the LDREX and STREX. The thing it does mention is about locking the memory bus which i guess is only helpful for MP systems where there can be more CPUs trying to access same location at same time. But for UP (and possibly MP), If a timer interrupt (or IPI for SMP) fires in this small window of LDREX and STREX, Exception handler executes possibly changes cpu context and returns to the new task, however the shocking part comes in now, it executes 'CLREX' and hence removing any exclusive lock held by previous thread. So how better is using LDREX and STREX than LDR and STR for atomicity on a UP system ?

我看过一些关于独占锁监视器，所以我一个可能的理论，即当线程简历和执行STREX，操作系统监视器导致此调用失败，可检测并可以重新执行循环在这个过程中（分支回LDREX）使用新的价值，我说的对吗？

I did read something about an Exclusive lock monitor, so I've a possible theory that when the thread resumes and executes the STREX, the os monitor causes this call to fail which can be detected and the loop can be re-executed using the new value in the process (branch back to LDREX), Am i right here ?

推荐答案

好吧，得到的答案从他们的<一个href=\"http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s02s01.html\">website.

Okay, got the answer from their website.

如果上下文切换的时间表已出所执行的过程之后的过程的下载专用，但它执行保存专用前，保存专用时，进程恢复，而内存则不会更新返回假阴性结果。这不会影响程序功能，因为这个过程可以立刻试操作。

If a context switch schedules out a process after the process has performed a Load-Exclusive but before it performs the Store-Exclusive, the Store-Exclusive returns a false negative result when the process resumes, and memory is not updated. This does not affect program functionality, because the process can retry the operation immediately.

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