多少也说明Linux内核，以处理上的ARM Cortex A9中断需要什么？ [英] How many instructions does Linux kernel need in order to handle an interrupt on an arm cortex A9?

问题描述

我想估计运算codeS的量需要一个 ARM 的Cortex A9 单核处理一个IRQ。

I would like to estimate the amount of opcodes it takes a ARM cortex A9 single core to handle an IRQ.

假设我与Linux内核工作 3.4 ，需要多少运codeS调用 IRQ 执行 irq_handler ？

Assuming I work with Linux kernel 3.4, how many opcodes it takes to call the irq and execute the irq_handler ?

推荐答案

您的问题是有关如何计算<一个href=\"http://stackoverflow.com/questions/14698229/what-is-the-irq-latency-due-to-the-operating-system\">interrupt延迟 的Linux。至少你可能会感兴趣的需要多长时间你的中断，甚至开始之前。我们会忽略这方面的的IRQ 在这里。

You question is related how to calculate the interrupt latency of Linux. At least you might be interested in how long it takes before your interrupt even starts. We will ignore this aspect of irqs here.

有一个简单的方法是一个切换 GPIO 和使用范围来衡量中断。你甚至可以切换 GPIO 多次看到时间不同阶段服用。这的Window CE链接展示了一个例子测量的延迟。有些中断控制器（如IMX）有I / O复用模式，其中一个中断号将提高/降低特定I / O线。或者，你可以添加code切换线（见下面的程序）。

A simple way is to toggle a GPIO and use a scope to measure the interrupt. You may even toggle the GPIO multiple times to see the time different phases take. This Window CE link shows an example measuring for latency. Some interrupt controller (such as the IMX) have I/O multiplexing modes where an interrupt number will raise/lower a particular I/O line. Alternatively, you can add code to toggle the line (see below for routines).

对于主中断处理的源代码在<一个href=\"http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/arm/kernel/entry-armv.S;hb=HEAD\"相对=nofollow>入门armv.S 。有您所使用的中断控制器定义的宏和这些依赖于的.config 文件。举例来说，有pre-先发制人中断，多中断控制器，SMP等的主要的载体在底部​​定义的入门armv.S 。一般的要点是，当前操作模式被检查，然后要么 __ irq_usr 或 __ irq_svc 拍摄。这些程序有不同的pre-充足的存储状态，但他们都最终调用了 irq_handler 宏。在 _irq_usr 拥有约 CMPXCHG 的东西，但如果指定，并在的ARM Cortex你的的.config ，这将不适用。主要的区别将是可能的上下文切换的IRQ在用户模式下发生之后。你的机器定义马赫/入门macro.S 这是汇编器宏来访问中断控制器，并得到一个中断号。然后，它跳转到通用 IRQ 处理code在顶层的内核的目录。

The source for the primary interrupt handling is in entry-armv.S. There are macros defined for the interrupt controller you use and these depend on the .config file. For instance, there is pre-emptive interrupts, multi-interrupt controllers, SMP, etc. The primary vectors are defined at the bottom of entry-armv.S. The general gist is that the current operating mode is inspected and then either __irq_usr or __irq_svc is taken. These routines have a different pre-ample to store state, but they both end up calling the irq_handler macro. The _irq_usr has stuff about cmpxchg, but if you specify and ARM cortex in your .config, this won't apply. The main difference will be the possible context switch after the IRQ occurs in user mode. Your machine defines mach/entry-macro.S which are assembler macros to access the interrupt controller and get an interrupt number. It then jumps to generic irq handling code in the top level kernel directory.

所以第二个方法是检查code和直接计算。这可能是比较容易，如果你看看源代码，编译内核，然后在的vmlinux 图片上做了一个 objdump的--disassemble ，并查找这些符号。你会看到扩大了 irq_handler 宏，它应该跳到你的IRQ code最后。

So the second way would be to inspect the code and calculate it directly. This is probably easier if you look at the source, compile your kernel and then do an objdump --disassemble on the vmlinux image and look for these symbols. You will see the irq_handler macro expanded and it should jump to your IRQ code eventually.

你可以从源头看，也有<一个href=\"http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=Documentation/irqflags-tracing.txt;hb=HEAD\"相对=nofollow> TRACE_IRQFLAGS 。您可以检查，看看是否可在您使用的做了Cortex A9 menuconfig的（和键入 / TRACE_IRQFLAGS ）。我不知道这是否是可用的。

As you can see from the source, there is also TRACE_IRQFLAGS. You can check to see if this is available on the Cortex A9 you are using with make menuconfig (and type /TRACE_IRQFLAGS). I don't know if it is available or not.

有变化，例如，

1. 从用户/ SVC模式中断。


2. 其它中断当前正在运行。

这被中断（如STM / LDM）
3. code可能需要一些时间才能完成。

在你的ISR
4. 页面错误。有些ALSA驱动可以至少在一些Linux版本未分配页故障。


5. 条件在你的ISR。

测量在示波器上会显示 IRQ 服务在抖动。检查指令通常将显示该 IRQ 可能永远不会被提供服务;例如，如果更高优先级的中断不断pre制止/ prevent的 IRQ 。也许你需要做既为硬限期全面优化。

Measuring on a scope will show the jitter in IRQ servicing. Examining the instructions will generally show that the IRQ may never be serviced; for example if higher priority interrupts constantly pre-empt/prevent the IRQ. Probably you need to do both to fully optimize for a hard deadline.

通常你不在乎多久整个 IRQ 需要，但 IRQ 行之间的时间被提出和写入/读取一些外设寄存器。例如， FIFO 可能深度有限，如果发生，读取IRQ之间的延迟的 FIFO 寄存器的值比 FIFO_Size点¯xBPS ，然后你有问题 FIFO 溢出。

Often you don't care how long the whole IRQ takes but the time between the IRQ line being raised and writing/reading some peripheral register. For instance, a FIFO may have limited depth and if the latency between the IRQ occurring and reading the FIFO register is greater than FIFO_Size x BPS, then you have issues with the FIFO overflowing.

的 FIQ 基础结构是快了很多，但你可以使用内核设施远不如！

The FIQ infra-structure is a lot faster, but the kernel facilities you can use are far less!

编辑：借助的Cortex A9技术参考有指令计数附录B中的大多数ARM指令是在大多数架构一个周期内，除了内存加载/存储，倍数和分支机构。按照第3和第4个以上的段落找到处理的Linux中断您的配置，只是完整指令路径添加了;为的预估的（因为原来的问题问）你可以算说明，它们通常是一个周期。

The Cortex A9 technical reference has instruction counts in appendix B. Most ARM instruction are a single cycle on most architectures, except memory load/store, multiples and branches. Follow the 3rd and 4th paragraphs above to find the complete instruction path to handle a Linux interrupt for your configuration and just add it up; for an estimate (as the original question asks) you can just count the instructions as they are generally a single cycle.

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