为什么＆QUOT;过程调用标准ARM体系结构＆QUOT; （AAPCS）要求SP为8字节对齐？ [英] Why "Procedure Call Standard for the ARM Architecture" (AAPCS) requires SP to be 8-byte aligned?

问题描述

由于这是一个经常性的话题，我把一个问题了。

根据 AAPCS ：

  

    

5.2.1.1通用协议栈的限制

    
    

    
• SP模4 = 0堆栈必须在任何时候都对齐到字边界

    

    
    

在一个公共接口5.2.1.2堆栈限制

    
    

    
• SPmod8 = 0的纸张都必须是双字对齐。

    

  

什么是落后8字节对齐合理？

解决方案

有许多可能的原因;

1. 工具从需要它。


2. LDRD / STRD 要求其在某些特定平台。


3. 许多ARM总线是64位宽。 8字节对齐会导致更快的内存访问。


4. 缓存也一致，一般宽度大于64位（128B，1024B）。


5. 页表与TLB将跨越超过64位（1K或4K +）更大的尺寸。


6. 标记指针可以例外使用（C ++，信号等）框架行走code。八个字节对齐允许要使用的附加比特。

的唯一一个重要的，标准是这么说的。你的编译器和工具将不能互操作，如果你不同意这个规定。主要项目1将意味着工具将不能互操作。在code将获取错误的值或一台机器会抛出异常。如果异常处理code利用项目5，也可能打破东西。

主要是，这一事实，有人作出的选择意味着人们可以利用这个事实的优势为他们喜欢使用什么都仍然互操作。编译器将遵循标准的意见，因为他们需要互操作与其他图书馆和可能没有被他们产生code。

同样重要的是要注意，这也适用于用于ARMv7 / A。用于Cortex M3（CM3_r0）的例子修订版本0未对齐SP以8项异常的多。

的ABIARM®架构咨询注意事项 - SP必须是8 - 字节在进入对准AAPCS - 符合功能

Since this is a recurring topic, I'm putting up a question about it.

According to AAPCS:

5.2.1.1 Universal stack constraints

• SP mod 4 = 0. The stack must at all times be aligned to a word boundary

5.2.1.2 Stack constraints at a public interface

• SP mod 8 = 0. The stack must be double-word aligned.

What is the rational behind 8-byte alignment?

解决方案

There are many possible reasons;

1. Tools from require it.
2. ldrd/strd require it on certain architectures.
3. Many ARM buses are 64bit wide. 8byte alignment will result in faster memory access.
4. Caches are also aligned and generally wider than 64 bits (128B, 1024b).
5. Page table and TLBs will straddle sizes larger than 64bits (1k or 4k+).
6. Tagged pointers can be used in exception (C++, signals, etc) frame walking code. The eight byte alignment allows for an additional bit to be used.

The only one that matters, The standard says so. Your compiler and tools will not inter-operate if you do not comply with this. Mainly item 1 will mean that the tools will not inter-operate. The code will fetch the wrong values or a machine exception will be thrown. If exception handling code makes use of item 5, it may also break things.

Mainly, that fact that someone made the choice means that people can take advantage of this fact for what ever use they like and still inter-operate. Compilers will follow the advice of the standard because they need to inter-operate with other libraries and code which may not have been generated by them.

It is also important to note that this applies to ARMv7/A. For example revision 0 of Cortex M3 (CM3_r0) does not align SP to a multiple of 8 on entry to exceptions.

ABI for the ARM® Architecture Advisory Note – SP must be 8 - byte aligned on entry to AAPCS - conforming functions

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