究竟什么是双处理器的问题？ [英] What exactly is a dual-issue processor?

问题描述

我碰到几个引用到的双发射的概念的处理器（我希望这甚至是有意义的句子）。我找不到究竟双重问题是任何解释。谷歌给我链接到微控制器的性能，但这个概念不被任何解释。这里有这样一个例子，<一个href=\"http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babbgjhi.html\">reference.我是不是找错了地方？它是什么一个简短的段落将是非常有益的。

I came across several references to the concept of a dual issue processor (I hope this even makes sense in a sentence). I can't find any explanation of what exactly dual issue is. Google gives me links to micro-controller specification, but the concept isn't explained anywhere. Here's an example of such reference. Am I looking in the wrong place? A brief paragraph on what it is would be very helpful.

推荐答案

双问题意味着每个时钟周期内处理器可以从管道向另一个的一个阶段移动两条指令。凡出现这种情况取决于处理器和公司的术语上：它可能意味着两个指令是从去code排队移动到排序队列（英特尔称之为这个问题），也可能意味着移动指令（或微操作或东西）从排序队列到执行端口（据我所知IBM称这个问题，而英特尔称之为调度）

Dual issue means that each clock cycle the processor can move two instructions from one stage of the pipeline to another. Where this happens depends on the processor and the company's terminology: it can mean that two instructions are moved from a decode queue to a reordering queue (Intel calls this issue) or it could mean moving instructions (or micro-operations or something) from a reordering queue to an execution port (afaik IBM calls this issue, while Intel calls it dispatch)

但实际上从广义上讲所以平时应意味着你可以保持每个周期执行2个指令。

But really broadly speaking it should usually mean you can sustain executing two instructions per cycle.

由于您标记此ARM，我想他们正在使用英特尔的术语。 Cortex-A8的和Cortex-A9可以，每个周期，取（在Thumb-2更）两条指令，德code两个指令和问题两个指令。在Cortex-A8的有没有乱序执行的，虽然我不记得是否有仍然是你发出一个去code排队 - 如果不是你从解码指令，将它们插入到两个执行管道直去。上的Cortex-A9有一个问题队列，所以德$ C $光盘指令发出有 - 则指令以高达4每个周期分派到执行管线

Since you tagged this ARM, I think they're using Intel's terminology. Cortex-A8 and Cortex-A9 can, each cycle, fetch two instructions (more in Thumb-2), decode two instructions, and "issue" two instructions. On Cortex-A8 there's no out of order execution, although I can't remember if there's still a decode queue that you issue to - if not you'd go straight from decoding instructions to inserting them into two execution pipelines. On Cortex-A9 there's an issue queue, so the decoded instructions are issued there - then the instructions are dispatched at up to 4 per cycle to the execution pipelines.

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