ARM LL / SC通过寄存器带宽或高速缓存线宽独占访问？ [英] ARM LL/SC exclusive access by register width or cache line width?

问题描述

我的工作我的lock-free的数据结构库的下一版本。

I'm working on the next release of my lock-free data structure library.

我用LL / SC ARM的。

I'm using LL/SC on ARM.

要使用LL / SC为LL / SC（而不是模拟CAS），必须有在LDREX和STREX之间的单一STR。

To use LL/SC as LL/SC (rather than emulating CAS) there has to be a single STR between the LDREX and STREX.

现在，我已经写了code和工作的。

Now, I've written the code and this works.

我关心的却是它可能无法正常工作的可能性。

What concerns me however is the possibility it may not work.

我读过PowerPC上，如果你访问相同的缓存行的LL / SC的目标，你打破了LL / SC。

I've read on PowerPC if you access the same cache line as the LL/SC target, you break the LL/SC.

所以我想，如果我的目标STR在同一高速缓存行作为我的LL / SC目标，那么战俘，我死了。

So I'm thinking if my STR target is on the same cache line as my LL/SC target, then pow, I'm dead.

现在，LL / SC目标和STR目标总是在不同的malloc（）如此他们直接在同一高速缓存行存在的机会可能是小（我可以通过浸轧LL / SC的目标以保本它开始的高速缓存行边界上并填充该高速缓存行）。

Now, the LL/SC target and STR targets are always in different malloc()s so the chance of them being directly in the same cache line is probably small (and I can guarantee this by padding the LL/SC target so it begins on a cache line boundary and fills that cache line).

但coud是假的共享，如果STR目标是恰到好处的（错了！）在内存中的地方。

But there coud be false sharing, if the STR target is in just the right (wrong!) place in memory.

纵观LDREX / STREX文档，这在descriibes物理地址来独占访问。这意味着注册宽度的粒度，不缓存线宽粒度。

Looking at the LDREX/STREX documentation, this descriibes exclusive access in terms of "the physical address". This implies register width granularity, not cache line width granularity.

这就是我的问题 - 就是内存访问LDREX / STREX灵敏度使用寄存器宽度粒度或高速缓存线宽的粒度？

And that's my question - is LDREX/STREX sensitivity to memory access using register width granularity or cache line width granularity?

推荐答案

ARM采用独家显示器来实现负载通过链接/条件存储到内存中独占访问。 [1]有所有的细节在这里我想说的重要性，如下：

ARM uses Exclusive Monitors to implement exclusive access to memory via load-linked/store-conditional. [1] has all the details, of importance here I'd say is the following:

独家预订颗粒

在专用监视器标签的地址，最小的区域，可以
  被标记为独占访问被称为独家预订
  颗粒（ERG）。该ERG是实现定义，范围8-2048
  字节，在两个字节的倍数。便携式code不应该假设
  任何事情ERG大小。

When an exclusive monitor tags an address, the minimum region that can be tagged for exclusive access is called the Exclusives Reservation Granule (ERG). The ERG is implementation defined, in the range 8-2048 bytes, in multiples of two bytes. Portable code must not assume anything about ERG size.

所以你有点运气了那里，我看到了。最真实的实现可能会保持一个较小的值无论如何，但它不是由基本ARM架构的，据我可以告诉保证的，但也许更有经验的人会发现我错了。 :)
尽管如此，还挺在那里LL / SC的所有实现都是某种形式的弱LL / SC的，所以你可以几乎从来没有完全确认LL和SC之间的商店并不总是杀SC，或大部分时间，或者从来没有...这只是这么多的架构和实现相关的，我个人坚持使用LL / SC实现CAS在紧密循环和使用，像往常一样，用它来完成。

So you're kinda out of luck there as I see it. Most real implementations will probably keep a small value anyway, but it's not guaranteed by the basic ARM architecture as far as I can tell, but maybe someone with more experience will find me wrong. :) Still, kinda all implementations out there of LL/SC are some form of weak-LL/SC, so you can almost never be completely sure that a store between the LL and the SC won't kill the SC always, or most of the time, or maybe never... It's just so much architecture and implementation dependent that I personally stick to using LL/SC to implement CAS in a tight loop and use that as usual and be done with it.

[1]的http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html

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