什么是更新ARM TTBR（翻译表基址寄存器）的缺点？ [英] What is the downside of updating ARM TTBR(Translate Table Base Register)?

问题描述

此问题是与此相关的：
<一href=\"http://stackoverflow.com/questions/27222060/while-forking-a-process-why-does-linux-kernel-copy-the-content-of-kernel-page\">While ＆QUOT;叉＆QUOT; ING一个过程，为什么Linux内核复制内核页表的每一个新创建的进程的内容

This question is related to this one: While "fork"ing a process, why does Linux kernel copy the content of kernel page table for every newly created process?

我发现，Linux内核试图避免通过交换技术的页表的内容复制到每个新创建的页表函数 pgd_alloc 。
问题是：什么是更新的下行ARM TTBR

I found that Linux kernel tries to avoid updating TTBR when switching between user land and kernel land by copying the content of swapper page table into every newly created page table in function pgd_alloc. Question is: What is the downside of updating ARM TTBR?

推荐答案

更​​新 TTBR （转换表基址寄存器）^注1 的MMU使有许多危险。有中断，缺页，TLB（MMU缓存）和L1和L2高速缓存加以考虑。在不同的系统，缓存也许PIPT或VIVT 的（物理或虚拟标记），有可能或不存在L1也不L2高速缓存。

Updating the TTBR (translation table base register)^Note1 with the MMU enables has many perils. There are interrupts, page faults, TLB (MMU-cache) and both L1 and L2 caches to be considered. On different systems, the caches maybe PIPT or VIVT (physically or virtually tagged), there may or may not exist L1 nor L2 caches.

人们似乎过分关注与MMU和TLB效率。他们总是在性能方面的考虑主要L1 / L2缓存相形见绌。这是一个较小的影响来更新MMU表并执行TLB刷新比它已经从L1 / L2 code和数据高速缓存未需要搬迁。至少一个TLB值得4KB或超过100个高速缓存行。在一些情况下，TLB条目也许1MB

People seem overly concerned about the MMU and TLB for efficiency. They are always dwarfed by the primary L1/L2 caches in performance considerations. It is a smaller impact to update the MMU tables and perform TLB flushes than it is to have un-needed evictions from the L1/L2 code and data caches. At a minimum a TLB is worth 4KB or over 100 cache lines. In some cases, the TLB entry maybe 1MB.

一些数据/ $ C $中的L1 / L2用户空间c可以需要在上下文切换到被逐出。然而，对于非常频繁的小工作负荷，一个用户上下文切换可保持code和数据中的L1 / L2。例如，一个媒体播放器做大量消耗CPU解码和一些的cron任务检查，没有看到新邮件在服务器上。交换机和背面从'的cron'任务可能导致剩余的L2高速缓存的视频解码使用code

Some data/code in the L1/L2 user space may need to be evicted on context switches. However, for very frequent small work-loads, a user context switch may keep code and data in the L1/L2. For example a media player doing large CPU intensive decoding and some cron task checking to see no new email is on a server. The switch to and back from the 'cron' task may result in code remaining in the L2 cache for the video decoding to use.

什么是更新的缺点ARM TTBR？

What is the downside of updating ARM TTBR?

除非自/至表是相同的，你必须保持内存的系统视图进行更新的时间是一致的。^注2 这自然会引起IRQ延迟和实现的复杂性，因为你需要同步处理了许多子系统。同时，Linux的MM（内存管理）code是架构无关。它可以处理各种各样MMU子系统。我们的目标是从来没有本地优化（在架构级），但在通用层优化全球。

Unless the from/to tables are identical you have to keep the system view of memory consistent for the duration of the update.^Note2 This will naturally cause IRQ latency and complexity of implementation as you need to sync up many sub-systems. Also, the Linux MM (memory management) code is architecture agnostic. It handles a great variety of MMU sub-systems. The goal is never to optimize locally (at the architecture level) but optimize globally at the generic layers.

注1：本 TTBR 是一个指针，它指向的是ARM MMU的第一层物理16K对齐的内存区域。每个条目为1MB（32位系统），并可能会指向另一个表;通常被称为L2。

Note1: The TTBR is a pointer to a physical 16k aligned memory region that is the first level of the ARM MMU. Each entry is 1MB (on 32bit systems) and may point to another table; often called L2.

注2：您可能在引导加载程序或者您正在迁移的存储设备之间的系统级code地做到这一点。即，更新具有相同表TTBR无关紧要本身。这是当表不同在于奇怪的事情会发生。

Note2: You might do this in a boot loader or places where you are migrating system level code between memory devices. Ie, update the TTBR with identical tables is of no consequence by itself. It is when the tables differ that weird things will happen.

这篇关于什么是更新ARM TTBR（翻译表基址寄存器）的缺点？的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！