将 16 位添加到 64 位寄存器 [英] add 16 bits to 64 bits register

问题描述

这是我想要做的:

   add     rsi, word [rsi+16]

我想读取位于 rsi+16 地址的无符号短值.我想将此值添加到 rsi.

I want to read the unsigned short value which is at rsi+16 adress. And i want to add this value to rsi.

这是我在 nasm 中得到的错误:

Here is the error i get in nasm:

s2.asm:62: error: mismatch in operand sizes

这很奇怪.为什么 nasm 和我的 cpu 无法将 16 位添加到 64 位寄存器?

This is strange. Why nasm and my cpu are not able to add 16 bits to 64 bits register ?

这是我所做的工作:

   mov     rbx,0
   mov     bx, word [rsi+16]
   add     rsi, rbx

这很奇怪，有没有最好的方法来做到这一点?

This is strange is there a best way to do that ?

谢谢

推荐答案

指令操作数必须具有相同的大小，除了符号和零扩展移动指令.

Instruction operands must have the same size, except sign and zero extend move instructions.

在您的情况下，您可以仅通过这种方式在一条指令中将 16 位添加到 64 位寄存器 rsi:

In your case, you can add 16 bits to 64 bits register rsi in one instruction only this way:

add si, word [rsi+16]

翻译成:

\x66\x03\x76\x10

因为si寄存器(size a word)是rsi寄存器的低位部分，所以可以加到si而不会干扰高位字节rsi.

Because si register(size a word) is a low part of rsi register, you can add to si without disturbing the upper bytes of rsi.

但它与 64 位加法的工作原理相同仅当 16 位加法结果不溢出时.例如:

But it will work the same as a 64-bit add only if the 16-bit add result doesn't overflow. For example:

假设我们有 esi=0x0000FFFF，我们将 si 加 1.我们有 esi=0x00000000.由于来自 16 位加法的进位，CF 将被设置.

Let's say we have esi=0x0000FFFF, and we add 1 to si. We've got esi=0x00000000. And CF will be set, because of carry-out from the 16-bit add.

如果您确实需要将进位传播到 RSI 的其余部分，请将零扩展到任何其他寄存器.

If you do need carry to propagate to the rest of RSI, zero-extend into any other register.

movzx  rax, word ptr [rsi+16]
add    rsi, rax

翻译成:

\x48\x0F\xB7\x46\x10
\x48\x01\xC6

<小时>

另外Ped7g指出:

但是您仍然会在某些架构上付出性能损失，当您将使用仅由 si 部分更新的完整 rsi 时，因此在性能方面最好还是先使用一些备用寄存器将字值扩展为 64b，然后添加两个 64b 寄存器(如果您将使用 rsi).

but you will still pay performance penalty on some architectures, when you will use full rsi which is partially updated by si only, so performance wise it is still better to use some spare register to extend the word value to 64b first, and then add two 64b registers (if you will use rsi).

另请参阅为什么 GCC 不使用部分寄存器?在 P6 系列 CPU 上写入 SI 然后读取 RSI 会导致性能问题，尽管这与 shellcode 漏洞利用负载无关.

See also Why doesn't GCC use partial registers? for possible performance issues from writing SI and then reading RSI on P6-family CPUs, although that's not relevant for shellcode exploit payloads.

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