无法使用 nasm 编译带有 xmmword 操作数大小的汇编代码 [英] Unable to compile assembly code with xmmword operand-size using nasm

问题描述

我试图使用 nasm(nasm -o file input.asm)编译汇编代码并在以下代码片段的第 2 行抛出错误:

I was trying to compile an assembly code using nasm (nasm -o file input.asm) and threw an error at line 2 in the following code snippet:

mov rsi, 0x400200
movdqu xmm0,xmmword [rsi]
nop

我不确定是否可以使用 nasm 编译具有 128 位寄存器的指令，但是在涉及 128 位寄存器的情况下，还有其他方法可以使用 nasm 进行编译吗?

I am not sure if instructions with 128 bit registers can be compiled using nasm but is there any other way to compile using nasm in such cases where 128 bit registers are involved?

推荐答案

内存操作数无需指定操作数大小，
只需使用 movdqu xmm0, [rsi] 并让 xmm0 表示 128 位操作数大小.
NASM 支持 SSE/AVX/AVX-512 指令.

You don't need to specify an operand size for the memory operand,
just use movdqu xmm0, [rsi] and let xmm0 imply 128-bit operand-size.
NASM supports SSE/AVX/AVX-512 instructions.

如果您确实想指定操作数大小，则 128 位的名称是 oword，根据 ndisasm 如果您汇编该指令然后反汇编结果机器码.oword = oct-word = 8x 2 字节字 = 16 字节.

If you did want to specify an operand-size, the name for 128-bit is oword, according to ndisasm if you assemble that instruction and then disassemble the resulting machine code. oword = oct-word = 8x 2-byte words = 16 bytes.

• tword、oword 和yword 操作数?
• QWORD 之后是什么?

注意 GNU .intel_syntax noprefix(由 objdump -drwC -Mintel 使用)将使用 xmmword ptr，与 NASM 不同.

Note that GNU .intel_syntax noprefix (as used by objdump -drwC -Mintel) will use xmmword ptr, unlike NASM.

如果您真的想使用 xmmword，请在文件顶部 %define xmmword oword.

If you really want to use xmmword, %define xmmword oword at the top of your file.

操作数大小总是由所有 SSE/AVX/AVX-512 指令的助记符和/或其他寄存器操作数暗示；我想不出任何需要指定 qword vs. oword vs. yword 或任何东西的指令，就像你用 movsx eax，字节 [rdi] 与 word [rdi].通常它与寄存器的大小相同，但有一些随机/插入/提取指令的例外.例如:

The operand-size is always implied by the mnemonic and / or other register operands for all SSE/AVX/AVX-512 instructions; I can't think of any instructions where you need to specify qword vs. oword vs. yword or anything, the way you do with movsx eax, byte [rdi] vs. word [rdi]. Often it's the same size as the register, but there are exceptions with some shuffle / insert / extract instructions. For example:

• SSE2 pinsrw xmm0, [rdi], 3 加载一个 word 并将其合并到 xmm0 的字节 6 和 7.
• SSE2 movq [rdi], xmm0 存储 qword 低半部分
• SSE1 movhps [rdi], xmm0 存储高 qword
• AVX1 vextractf128 [rdi], ymm0, 1 对高半部分进行 128 位存储
• AVX2 vpmovzxbw ymm0, [rdi] 从 128 位内存源操作数执行压缩字节 -> 字零扩展
• AVX-512F vpmovdb [rdi]{k1}, zmm2 将 dword 缩小到字节元素(带有截断；其他版本会饱和)并执行 128 位存储，并在字节粒度进行屏蔽.(在没有 AVX-512BW 的情况下进行字节粒度屏蔽的唯一方法之一，除了具有缓存驱逐 NT 语义的 legacy-SSE maskmovdqu.所以我想这对 Xeon Phi KNL 来说特别有趣.)

• SSE2 pinsrw xmm0, [rdi], 3 loads a word and merges it into bytes 6 and 7 of xmm0.
• SSE2 movq [rdi], xmm0 stores the qword low half
• SSE1 movhps [rdi], xmm0 stores the high qword
• AVX1 vextractf128 [rdi], ymm0, 1 does a 128-bit store of the high half
• AVX2 vpmovzxbw ymm0, [rdi] does packed byte->word zero extension from a 128-bit memory source operand
• AVX-512F vpmovdb [rdi]{k1}, zmm2 narrows dword to byte elements (with truncation; other versions do saturation) and does a 128-bit store, with masking at byte granularity. (One of the only ways to do byte-granularity masking without AVX-512BW, other than legacy-SSE maskmovdqu which has cache-evicting NT semantics. So I guess that makes it especially interesting for Xeon Phi KNL.)

您可以在其中任何一个上指定 oword 以确保内存访问的大小与您认为的一样.(即让 NASM 为您检查.)

You could specify oword on any of those to make sure the size of the memory access is what you think it is. (i.e. to have NASM check it for you.)

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