移动二维数组的Verilog [英] Shifting 2D array Verilog

问题描述

我不知道什么犯规以下code的工作，但它不会合成：

I dont know what doesnt work on the following code, but it wont synthesize:

reg [7:0] FIFO [0:8];

always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in, FIFO[1:8]};
    end
end

我试图指数FIFO其他方式也一样，但没有任何工程。发现这个话题在Xilinx论坛，但我只是不能figue出他想告诉有什么。这里是链接：

I tried to index the FIFO other ways too, but nothing works. Found this topic on a Xilinx forum but I just cant figue out what he wanted to tell with that. Here is the link:

<一个href=\"http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368\" rel=\"nofollow\">http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368

感谢

推荐答案

您有怎样带包装阵列工作的小姐认识。我建议你​​阅读IEEE1800-2012部分7.4.1，7.4.2，7.4.4，＆安培; 7.4.5。技术上IEEE1800是SystemVerilog的是一个超集的Verilog。这两个是静态数组的大小相同，我觉得IEEE1800有一个更好的解释和实例然后IEEE1364。

You have a miss understanding of how packed and unpacked arrays work. I recommend you read the IEEE1800-2012 section 7.4.1, 7.4.2, 7.4.4, & 7.4.5. Technically IEEE1800 is for SystemVerilog which is a super set of Verilog. The two are the same for arrays with static sizes and I find IEEE1800 has a better explanation and examples then the IEEE1364.

如果您还没有LRM的副本，那么您可以在ieee.org网站免费下载：的 http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

If you don't already have a copy of the LRM, then you can download it for free at the ieee.org website: http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

有关提供的code，你不能每一个元素，在这种方式的解压数组分配。你有两个选择：使用一个for循环指定数组的解压部分，或者使你的阵列双层包装

For the provided code, you cannot assign every element in an unpacked array in that manner. You have two choices: Use a for-loop to assign the unpacked portion of the array, or make your array double packed.

/* Using for-loop */
reg [7:0] FIFO [0:8];
integer i;
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       for(i = 8; i > 0; i=i-i) begin
          FIFO[i] <= FIFO[i-1];
       end
       FIFO[0] <= data_in;
    end
end

/* Using double packed array */
reg [0:8] [7:0] FIFO; // NOTE: format and usage explained in IEEE1800-2012 7.4.5
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in,FIFO[0:7]};
    end
end

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