填写二维数组一行进程外(VHDL) [英] Fill one row in 2D array outside the process (VHDL)
问题描述
我有数组:
type MATR is array(natural range 1 to N, natural range 1 to N) of natural;
signal m: MATR;
1)是否有可能以填充元素M(0,1),M(0,2)...... M(O,N)与过程之外的一些值?是这样的:
1) Is it possible to fill elements m(0, 1), m(0, 2) ... m(0, N) with some value outside of process? Something like:
m(1) <= (others => 2)
2)是否有可能分配一维数组(范围为1〜N)以二维数组一行(外还加工的)?
2) Is it possible assign 1D array(range 1 to N) to one row of 2D array (Also outside of process)?
推荐答案
是的,你可以通过写这样一个过程做到这一点:
Yes you can do this by writing a procedure like this one:
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE XST/iSim 14.2
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
在哪里T_SLM是这样定义我的矩阵类型:
Where T_SLM is my matrix type defined like this:
-- STD_LOGIC_MATRIXs
type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSim, vSim, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM work-around: DON'T use myMatrix'range(n) for n >= 2
-- because: myMatrix'range(2) returns always myMatrix'range(1); tested with ISE/iSim 14.2
-- USAGE NOTES:
-- dimension 1 => rows - e.g. Words
-- dimension 2 => columns - e.g. Bits/Bytes in a word
因此,这里是使用这个程序的例子:
So here is an example to use this procedure:
architecture [...]
signal myVector : STD_LOGIC_VECTOR(7 downto 0);
signal myMatrix : T_SLM(3 downto 0, myVector'range) := (others => (others => 'Z'));
[...]
begin
[...]
assign_row(myMatrix, myVector, 0);
assign_row(myMatrix, (myVector'range => '0'), 1);
assign_row(myMatrix, x"4A", 2);
[...]
end;
这code与ISE XST和的iSim(13.x,14.x),VSIM和GHDL测试。作为ISE 13.x是当前版本中,赛灵思表示,范围,错误将不会被固定在ISE 14.x。
This code is tested with ISE XST and iSim (13.x, 14.x), vSim and GHDL. As ISE 13.x was the current release, Xilinx stated that the range-bug will not be fixed in ISE 14.x.
如果您需要周围的其他方法,这里是我的功能get_row:
If you need the other way around, here is my function get_row:
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSim work-around, because 'range(2) = 'range(1); tested with ISE/iSim 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
如果你想使用自然的,因为基本型为向量和矩阵,然后用自然科学交换STD_LOGIC。
If you want to use NATURAL as the elementary type for the vectors and matrices, then exchange STD_LOGIC with NATURAL.
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