<<模块名称>>不是 verilog 中的任务或无效函数 [英] <<module name>> not a task or void function in verilog

问题描述

我正在尝试在 verilog 中创建一个用于进位选择加法器的模块.除了以下部分导致编译错误外，一切正常.

I am trying to create a module for carry select adder in verilog. Everything works fine except the following portion where it is causing compilation error.

module csa(a,b,s,cout);
input[15:0] a,b;
output [15:0] s;
output cout;
wire zero_c1, zero_c2,zero_c3,zero_c4,zero_c5;
wire one_c1, one_c2,one_c3,one_c4,one_c5;
wire temp_c1,temp_c2,temp_c3,temp_c4,temp_c5;
wire [15:0] s_zero, s_one;

initial
begin
fork
    fa(s[0], temp_c1,a[0],b[0],0);
    fa_one(s_zero[1],s_one[1],zero_c1,one_c1,a[1],b[1]);
    fa_two(s_zero[3:2],s_one[3:2],zero_c2,one_c2,a[3:2],b[3:2]);
    fa_three(s_zero[6:4],s_one[6:4],zero_c3,one_c3,a[6:4],b[6:4]);
    fa_four(s_zero[10:7],s_one[10:7],zero_c4,one_c4,a[10:7],b[10:7]);
    fa_five(s_zero[15:11],s_one[15:11],zero_c5,one_c5,a[15:11],b[15:11]);
join
end

当我尝试编译时，它说 -

When I try to compile that it says -

模块fa"、fa_one"不是任务或无效函数

the module "fa", "fa_one" are not a task or void function

我删除了初始"语句，现在它说 -

I deleted the "initial" statement and now it says -

fork"附近的语法错误，应为endmodule"

Syntax error near "fork", expecting "endmodule"

我只想在 join 和 fork 之间并行运行代码.我也确认模块 fa, fa_one 工作正常.

I just want to run the code between join and fork in parallel. I have also confirmed that the module fa, fa_one works fine.

如果有人能帮我指出我在这里做错了什么，我将不胜感激.谢谢.

Would appreciate if anyone can help me pointing out what I am doing wrong here. Thanks.

推荐答案

Verilog 模块不是运行或执行而是实例化，它们代表硬件的物理块.

Verilog modules are not run or executed but instantiated, they represent physical blocks of hardware.

除非您努力分时共享硬件，否则一切都是并行的.例如，您可能会编写一个 ALU 内核，它只存在一次，但使用程序 ROM 告诉它每个时钟周期处理哪条指令.

Everything is in parallel unless you have made effort to time share pieces of hardware. For example you might write an ALU core, which exists only once but use a program ROM to tell it which instruction to process every clockcycle.

在您的模块中，您可以拥有组合代码和顺序代码.

Inside your modules you can have combinatorial code and sequential code.

组合 逻辑将在 0 时间内进行模拟，但实际上将值放置在真实设备上时需要一些时间来传播.

Combinatorial logic will simulate in 0 time but will actually take some time for values to propagate through when placed on real devices.

如果不考虑这种传播延迟并且创建了非常大的逻辑块，您将很难在综合时关闭时序，因为通过逻辑的稳定时间大于组合逻辑任一侧的时钟速度.

If this propagation delay is not thought about and very large blocks of logic are created you will struggle to close timing on synthesis, due to the settling time through the logic being greater than the clock speed either side of the combinatorial logic.

顺序 逻辑意味着结果保存在触发器中，触发器仅在时钟边沿更新.这意味着时序逻辑链可能需要许多时钟周期才能传播数据.

Sequential logic implies that the results are held in flip-flops, which only update on clock edges. This means chains of sequential logic can take many clock cycles for data to propagate.

在对处理器进行流水线处理时，您用触发器将各个部分分开，为每个部分提供一个完整的时钟周期进行组合传播，代价是需要花费几个时钟周期来计算单个结果.

When pipelining a processor you break individual section up with flip-flops giving each section a full clock cycle for combinatorial propagation, at the expense of taking several clock cycles to calculate a single result.

要纠正您的示例，您只需:

To correct your example you would just have:

module csa(
  input  [15:0] a,
  input  [15:0] b,
  output [15:0] s,
  output        cout
);
wire zero_c1, zero_c2,zero_c3,zero_c4,zero_c5;
wire one_c1, one_c2,one_c3,one_c4,one_c5;
wire temp_c1,temp_c2,temp_c3,temp_c4,temp_c5;
wire [15:0] s_zero, s_one;

fa       ufa(s[0], temp_c1,a[0],b[0],0);
fa_one   ufa_one(s_zero[1],s_one[1],zero_c1,one_c1,a[1],b[1]);
fa_two   ufa_two(s_zero[3:2],s_one[3:2],zero_c2,one_c2,a[3:2],b[3:2]);
fa_three ufa_three(s_zero[6:4],s_one[6:4],zero_c3,one_c3,a[6:4],b[6:4]);
fa_four  ufa_four(s_zero[10:7],s_one[10:7],zero_c4,one_c4,a[10:7],b[10:7]);
fa_five  ufa_five(s_zero[15:11],s_one[15:11],zero_c5,one_c5,a[15:11],b[15:11]);
endmodule

注意:它是 module_name #(parameters) instance_name ( ports );

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