系统 verilog 正则表达式 [英] System verilog Regular expressions

问题描述

我知道系统 verilog 没有很好的内置正则表达式支持.

I understood that System verilog does not have very good regular expression support inbuilt.

如何在 systemVerilog 中检查 srting 是否与以下正则表达式匹配:"\d+(ns|ps|us)"

How can I check in systemVerilog that a srting matches to the following regular expressions: "\d+(ns|ps|us)"

推荐答案

您有许多不同的选择.

一些模拟器已经支持一组 SystemVerilog 字符串方法扩展，用于处理 str.match() 和 str.search() 等正则表达式.

Some simulators already support a set of SystemVerilog string method extensions that handle regular expressions such as str.match() and str.search().

result = str.match("pattern"); // returns true if the pattern is matched with the str.

如果您使用的是 UVM，有一个 DPI 例程可以做同样的事情

If you are using the UVM, there is a DPI routine that does the same thing

result = uvm_pkg::uvm_re_match("pattern",str);

还有许多其他软件包，例如 SVunit，它们也为您提供 DPI 例程.

There are number of other packages out there such as SVunit that also provide the DPI routines for you.

这篇关于系统 verilog 正则表达式的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！