在(系统)verilog 模拟中从命令行定义参数 [英] Defining parameters from command line in (system)verilog simulation
问题描述
我有一个模块受约束",有几个延迟作为参数.我想模拟模块中所有可能的延迟配置.
I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module.
由于我有很多配置要测试,我不想在同一个测试平台中实例化所有可能的配置.
As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench.
我的想法是为每个配置启动一个模拟.
The idea I had was to launch one simulation for each configuration.
我想过生成一个模拟脚本,为每个延迟配置启动模拟.问题是我无法使用从命令行检索到的值来覆盖模块的参数.
I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line.
我使用了 $value$plusargs("ARG=%d",val)
并且 val
是变量的事实与后来的 defparam 不兼容代码>.
I used $value$plusargs("ARG=%d",val)
and the fact that val
is a variable is incompatible with the later defparam
.
最完美的方法是从命令行参数创建定义或 localparam,但我在研究中没有找到任何相关信息.
The perfect thing would be to create a define, or a localparam from the command-line argument but I did not find anything about it in my research.
我也乐于接受任何有关进行这些模拟的另一种方法的建议,也许更有效,因为我认为这样做需要很长时间.
I am also open to any suggestion about another way to doing these simulation, maybe more efficiently, because I think that this will be quite long to do it that way.
PS:为了避免为每个配置重新编译和重新启动模拟器,我还考虑在每种情况下重新实例化测试模块.然而,我认为(系统)verilog 是不可能的.
PS: To avoid recompiling and re-lauching the simulator for each configuration I also thought about re-instantiating the tested module in each case. I however do not think that it is possible with (system)verilog.
推荐答案
Modelsim/Questa 允许您从仿真命令行覆盖参数,但这样做会降低仿真性能.寻找 vsim -Gparamname
选项.
Modelsim/Questa allows you to override parameters from the simulation command line, but does so as some cost in simulation performance. Look for the vsim -Gparamname
option.
在您的情况下,如果您可以使用这些延迟的变量而不是参数来编写模块,然后使用 $value$plusargs
直接设置它们会更好.
In your case, it would be much better if you could write your modules using variables for these delays instead of parameters, then use $value$plusargs
to set them directly.
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