八位除法器:商和余数 [英] Eight Bit Divider: Quotient and Remainder

问题描述

我正在尝试调试下面显示的代码.我对 SystemVerilog 还很陌生，希望我能从中学习.让我知道任何建议.

我收到的错误是:

Error-[ICPD] 无效的程序驱动组合"divide.v", 2变量Q"由无效的程序驱动程序组合驱动.写在always_comb"左边的变量不能被任何人写入其他进程，包括其他always_comb"进程."divide.v", 2: 逻辑 [7:0] Q;"divide.v", 8: always_comb begin如果 (x <= R) 开始..."divide.v", 5: Q = 8'b0;错误-[ICPD] 无效的程序驱动程序组合"divide.v", 2变量R"由无效的程序驱动程序组合驱动.写在always_comb"左边的变量不能被任何人写入其他进程，包括其他always_comb"进程."divide.v", 2: 逻辑 [7:0] R;"divide.v", 8: always_comb begin如果 (x <= R) 开始..."divide.v",6: R = y;

我的 SystemVerilog 代码是:

模块分频器(输入逻辑[7:0] x,y,输出逻辑 [7:0] Q,R);最初的开始Q = 8'd0;R = y;结尾always_comb开始如果 (x<=R)开始 R <= R - x;Q＜=Q+8'd1;结尾结尾结束模块模块测试1；逻辑 [7:0] x,y,Q,R;分频器分频器 1 (x,y,Q,R);最初的开始x = 8'd2;y = 8'd8;结尾结束模块

解决方案

通常，在 Verilog/SystemVerilog 中，您不能将两个并行块中的变量分配给变量(有一些例外).您从两个位置分配给 R 和 Q:initial 块和 always_comb 块.

虽然initial块只运行一次，但在模拟开始时与always_comb块并行运行，违反了此规则.>

为什么不去掉 initial 块并在 always_comb 中做所有事情?

 always_comb开始Q = 8'd0;//设置Q的初始值R = y;//设置R的初始值....//算法的其余部分结尾

此外，您缺少使用循环！

I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.

The errors I am receiving are:

Error-[ICPD] Invalid procedural driver combination
"divide.v", 2
Variable "Q" is driven by an invalid combination of procedural drivers. 
Variables written on left-hand of "always_comb" cannot be written to by any 
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] Q;
"divide.v", 8: always_comb  begin
if (x <= R) begin
...
"divide.v", 5: Q = 8'b0;

Error-[ICPD] Invalid procedural driver combination 
"divide.v", 2
Variable "R" is driven by an invalid combination of procedural drivers. 
Variables written on left-hand of "always_comb" cannot be written to by any 
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] R;
"divide.v", 8: always_comb  begin
if (x <= R) begin
...
"divide.v",6: R = y;

My SystemVerilog Code is:

module divider(input  logic [7:0] x,y,
               output logic [7:0] Q,R);
  initial
    begin
      Q = 8'd0;
      R = y;
    end
  always_comb
    begin
      if (x<=R)
        begin R <= R - x; Q <= Q + 8'd1; end
    end
endmodule

module test1; 

  logic [7:0] x,y,Q,R;

  divider Divider1 (x,y,Q,R);

  initial 
    begin
      x = 8'd2;
      y = 8'd8;
    end
endmodule

解决方案

Generally, in Verilog/SystemVerilog you cannot assign to a variable from two parallel blocks (with some exceptions). You are assigning to R and Q from two places: the initial block and the always_comb block.

Although the initial block only runs once, it runs in parallel with the always_comb block at the beginning of the simulation, which is a violation of this rule.

Why don't you get rid of the initial block and do everything in always_comb?

   always_comb
    begin
      Q = 8'd0;     // set initial value of Q
      R = y;        // set initial value of R
      ....          //THE REST OF THE ALGORITHM
    end

Also, you are missing using a loop!

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