非法类型转换 VHDL [英] Illegal type conversion VHDL

问题描述

我试图通过 vhdl 中的类型转换返回类型 std_logic_vector.这是我的代码:

I was trying to return type std_logic_vector by type conversion in vhdl. Here is my code:

 function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is
    variable v_TEST_VARIABLE1 : integer;
    variable v_TEST_VARIABLE2 : integer;
    variable n_times: integer:=1;
    variable product: integer:=0;
    begin 
      for n_times in 1 to v_TEST_VARIABLE2 loop
        product:=product + v_TEST_VARIABLE1;
      end loop;
    return std_logic_vector(product);
  end mul;

它在编译时给出从 std.standard.integer 到 ieee.std_logic_1164.std_logic_vector(数字到数组)的非法类型转换.".如何在这样的代码中返回 std_logic_vector?

It gives "Illegal type conversion from std.standard.integer to ieee.std_logic_1164.std_logic_vector (numeric to array)." on compilation. How do I return std_logic_vector in such a code?

推荐答案

您必须先将其转换为无符号.我希望你使用的是 numeric_std?如果是这样，您的代码如下所示.请注意，要使用 to_unsigned，您必须知道输出 std_logic_vector 的长度.因此，这要么需要作为您的函数的输入，要么您可以绑定返回向量:

You must first convert it to an unsigned. I hope you're using numeric_std? If so, your code looks like this. Note that to use to_unsigned you must know the length of your output std_logic_vector. So this either needs to be an input to your function or you can bound the return vector:

return std_logic_vector(to_unsigned(product, length));

有关如何将 std_logic_vector 转换为整数.

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