分配的Verilog整个阵列 [英] Assigning entire array in verilog

问题描述

我想一个二维数组复制到另一个像这样：

I am trying to copy a 2d array into another like so:

reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1]; 
reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1];
always @(posedge clk)
begin
     if(<some condition>)
          output_matrix <= input_matrix;
end

因此​​，我们有12位值的两个二维数组。我想复制一个到另一个。

So, we have two 2D arrays of 12-bit values. I'd like to copy one into the other.

这似乎并不可能。有谁知道正确的方式做到这一点？或者，如果不是，解释为什么这是不可能的？我看不出有任何理由这项任务将无法合成。

This doesn't seem to be possible. Does anyone know the correct way to do this? Or, if not, explain why it's not possible? I can't see any reason why this assignment wouldn't be able to synthesize.

有关循环一般不合成好，原因是显而易见的。然而，就是一个for循环可以使用情况下，这一个，因为该循环静态定义？

For loops generally don't synthesize well, for obvious reasons. However, is this one of the cases that a for loop can be used, because the loop is statically defined?

推荐答案

由于@toolic提到为循环是综合的。这种情况是它是完全正常的，因为它可以静态地展开。

As @toolic has mentioned for loops are synthesizable. This is the case were it is perfectly fine as it can be statically unrolled.

内环可能不是必要的，但我发现的综合工具版本的一些记忆（阵列）分配挣扎着，他们的工作，但改名为公交车严重可导致ECO的问题。

The inner loop may not be necessary but I find some version of synthesis tools struggled with memory (array) assignments, they worked but renamed the buses badly which can cause issues with ECO's.

reg [11:0] input_matrix  [0:array_width - 1] [0:array_height - 1]; 
reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1];
integer i;
integer j;

always @(posedge clk) begin
  if(<some condition>) begin
    for (i=0; i<array_width; i=i+1 ) begin
      for (j=0; j<array_height; j=j+1 ) begin
        output_matrix[i][j] <= input_matrix[i][j];
      end
    end
  end
end

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