<信号>不是常数"if 语句中的错误 [英] "<signal> is not a constant" error in if-statement

问题描述

我正在尝试编写一个简单的模块来根据四个输入信号的值输出一个 14 位数字.我的尝试如下所示.

I am trying to write a simple module to output a 14-bit number based on the value of four input signals. My attempt is shown below.

module select_size(
    input a,
    input b,
    input c,
    input d,
    output [13:0] size
);

    if (a) begin
        assign size = 14'h2222;
    end
    else begin
        if (b) begin
            assign size = 14'h1111;
        end
        else begin
            if (c) begin
                assign size = 14'h0777;
            end
            else begin
                assign size = 14'h0333;
            end
        end
    end

endmodule

在编译时，我收到以下错误:

Upon compilation, I receive the following error:

ERROR:HDLCompiler:44 - Line 67: c 不是常量

ERROR:HDLCompiler:44 - Line 67: c is not a constant

我不明白为什么如果前面的其他两个语句有效，那么特定的 if 语句不起作用.我已尝试将条件更改为

I don't understand why that particular if-statement isn't working if the other two preceding it are. I have tried changing the condition to

if (c == 1) begin

但无济于事.

有人知道如何解决这个错误吗?谢谢！

Does anybody know how to solve this error? Thank you!

推荐答案

两个问题:

1) 您需要将 if 语句放在 always 块中.

1) You need to put if statements inside an always block.

如果你使用verilog-2001，你可以使用

If you use verilog-2001, you can use

always @*
   if ....
   end
end

否则指定敏感度列表中的所有输入:

Otherwise specify all the inputs in the sensitivity list:

always @(a or b or c or d)
   if ....
   end
end

<小时>2) if 语句中不允许使用常量赋值.

---

2) Constant assignments are not allowed inside if statements.

从 if 块内的任何语句中删除 assign 关键字:

Remove the assign keyword from any statements inside the if block:

if (a) begin
    size = 14'h2222;
end

您还必须将 size 声明为 reg 类型.

You will also have to declare size as a reg type.

然而，我更喜欢用条件运算符重写整个模块，我发现它更适合阅读.以下模块实现了相同的结果:

However my preference would be to rewrite the entire module with conditional operator, I find it much preferrable to read. This following module achieves the same result:

module select_size(
    input a,
    input b,
    input c,
    input d,
    output [13:0] size
);

    assign size = a ? 14'h2222 :
                  b ? 14'h1111 :
                  c ? 14'h0777 : 
                      14'h0333 ;

endmodule

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