在 verilog 中使用 always 块时出错 [英] Error while using always block in verilog

问题描述

我在verilog中有一个模块temp1，如下所示，-

I have a module temp1 in verilog say as below,-

module temp1;
---
---
---
endmodule

我想从其他模块 temp2 调用这个模块实例.但是，我想在时钟的正沿进行此定律-

I want to call this module instance from other module temp2. However, I want to this laways at the positive edge of the clock-

module temp2(clk);
    input clk;
    always @(posedge clk)
        temp1 t1;
endmodule

这给了我语法错误.看来我不应该从 always 块中调用任何模块.我们不能从 always 块中创建模块的实例是真的吗?如果是，我怎么能以其他方式做到这一点，因为我必须在时钟的边缘调用 temp1?

This gives me syntax error. It seems I should not call any module from within the always block. Is it true that we cannot create instance of a module from within the always block? If yes, how can I do this in some other way as I have to call temp1 only when at the posedge of the clock?

推荐答案

在 verilog 中，当您实例化一个模块时，这意味着您正在向模块添加额外的硬件板.

In verilog, when you are instantiating a module, that means you are adding extra hardware to the board.

此硬件必须在模拟开始前(即在编译时)添加.在这里，您可以不在每个时钟脉冲上添加/删除硬件.

This hardware must be added before simulation starts(i.e. at compile time). Here, you can not add/remove hardware at each clock pulse.

一旦实例化，就会针对每个时间戳的模拟执行/检查模块，直到结束.

Once instantiated, the module is executed/checked for each timestamp of simulation, till the end.

因此要执行任何模块，只需将其实例化，为其提供时钟和其他所需的输入，然后在子模块本身中添加 always 块.

So to execute any module, just instantiate it, providing the clk and other required inputs to it, and add the always block in the sub-module itself.

module temp2(clk);
    input clk;
        temp1 t1(clk); // note the input port clk here
endmodule

module temp(input clk);
    always @(posedge clk)
    begin
    // ...
    end
endmodule

Verilog 提供了一个生成块，用于创建同一模块的多个实例.

Verilog provides a generate block for creating multiple instances of the same module.

genvar i;  // note special genvar type, used in generate block
generate
for(i=0;i<5;i++)
temp t1[i];  // create 5 instances of temp module
endgenerate

旁注:

您可能混淆了对模块实例化和任务/函数的调用的理解.模块是一个静态实体，而任务/功能可以是动态实体.正如你所展示的，如果 temp 是一个任务，那么上面的调用是有效的.

You may have mixed the understanding about module instantiation and calling of task/function. Module is a static entity while task/function can be dynamic ones. As you showed, if temp is a task, then the above call is valid.

task temp;
// ...
endtask: temp

module temp2(clk);
    input clk;
    always @(posedge clk)
        temp1(); // task/function temp
endmodule

关于实例化的更多信息可以从Verilog Module Instantiation 获得, 实例化模块和基元，结构建模链接.

More information on instantiation can be obtained from Verilog Module Instantiation, Instantiating Modules and Primitives, Structural Modelling links.

这篇关于在 verilog 中使用 always 块时出错的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！