当 if(a) 在 Verilog 中返回 true 时 [英] when if(a) will return true in Verilog

问题描述

我是 Verilog 的新手，有人问我以下问题:

I am new to Verilog and I had been asked the following question:

考虑a = reg[3:0]，那么a可以有什么值，所以if(a)会返回真的?我不知道从哪里开始，试图编译一些例子但都失败了syntax problem.

Consider a = reg[3:0], then what values can a have so if(a) will return true? I have no idea where to start, tried to compile some examples but all failed syntax problem.

推荐答案

写if (a)和写if (a !=0)是一样的.由于 a 是一个 4 位变量，您可以将其扩展为 if (a[0] != 0 | a[1] != 0 | a[2] != 0| a[3] !=0).因此，任何位位置的 1 都会使表达式为真.请注意，未知值 x 或 z 作为具有相等/不等式运算符的操作数会导致未知值并被视为错误.但是一个未知的 or'ed with true 是 true.

Writing if (a) is the same as writing if (a !=0). Since a is a 4-bit variable, you can expand that out to if (a[0] != 0 | a[1] ! = 0 | a[2] != 0 | a[3] !=0). So a 1 in any bit position makes the expression true. Note that an unknown value x or z as an operand with the equality/inequality operators results in an unknown and is considered false. But an unknown or'ed with true is true.

这篇关于当 if(a) 在 Verilog 中返回 true 时的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！