Verilog 显示中不必要的空格 [英] Unnecessary spaces in Verilog Display

问题描述

我正在尝试以十进制显示一些 32 位值，除了我的 %b 和前一个字符之间奇怪数量的不必要的空格之外，这工作正常.

I'm trying to display some 32 bit values in decimal, and this is working fine other than the strange amount of unecessary spaces between my %b and the previous character.

例如:如果我有一个十进制值为 33 的 32 位 reg a，我将使用类似这样的东西

for example: if i have a 32-bit reg a with a decimal value of 33, i'll use something like this

initial
begin
    $display("a=%d;", a);
end

cmd 中的输出类似于以下内容:a= ___________________33;

the output in cmd would look similar to this: a= ___________________33;

该行仅表示 %b 和前一个字符之间的长空格.有人可以向我解释为什么会发生这种情况吗?我怎样才能摆脱它们?

The line just represents the long blank space between %b and the previous char. Can somebody explain to me why this happens? And how can I get rid of them?

推荐答案

在 IEEE Std 1800-2012 (21.2.1.3) 您可以找到以下信息:

In IEEE Std 1800-2012 (21.2.1.3) you can find following information:

显示十进制值时，前导零被抑制并替换为空格.在其他基数中，始终显示前导零.

When displaying decimal values, leading zeros are suppressed and replaced by spaces. In other radices, leading zeros are always displayed.

这就是为什么你在 33 之前有这么多空格.实现您想要的目标的最简单方法是:

That's why you got so many spaces before 33. The simplest way to achieve whay you want would be:

$display("a=%0d;", a);

通过在% 字符和d(指示基数的字母)之间添加0，显示数据的自动调整大小将被覆盖.结果将以尽可能小的尺寸打印.

By adding 0 between % character and d (letter that indicates the radix) the automatic sizing of displayed data is overridden. The result will be printed with minimum possible size.

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