如何修复实例上的错误:未定义的变量 B? [英] How do I fix the error on instance: Undefined variable B?

问题描述

我想编译这个 Verilog 代码，但我在 MultiP 模块中的 B 模块实例中出错:

I want to compile this Verilog code, but I had errors in the instance of the B module in the MultiP module:

error 1: Undefined variable B.
error 2: near "Adder1": syntax error, unexpected IDENTIFIER.

代码:

 module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;  
     reg co,sum;

     always @(x | y | ci)
       begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end  
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

  always @(x | y | ci | ppk)
    begin
      A((x & y),ppk,ci,co,ppko);
   end 
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

  always @(x | y )
  begin

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );
  
  end    
              
endmodule

推荐答案

我对您的代码进行了最小的更改以使其能够编译:

I made minimal changes to your code to get it to compile:

module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;
     reg co,sum;

     always @* begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

    A A ((x & y),ppk,ci,co,ppko);
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );
endmodule

正如 Marty 提到的，我用 * 替换了模块 A 中的 always 块敏感列表.我摆脱了 A 和 B 实例周围的总是块.我为 A 实例添加了一个实例名称.

As Marty mentioned, I replaced the always block sensitivity list In module A with *. I got rid of the always blocks around your A and B instances. I added an instance name for the A instance.

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