从现有总线形成正交总线组(而不是行总线、列总线) [英] Form orthongonal group of busses from existing bus (instead of busses of the rows, busses of the columns)

问题描述

我有这样的输入进入模块:

I have inputs like this coming into a module:

   input  wire [31:0]     row0_Q,
   input  wire [31:0]     row1_Q,
    ...
   input  wire [31:0]     row30_Q,
   input  wire [31:0]     row31_Q

并且由于缺乏更好的术语而想要形成列"的总线.我可以做很长的路:

and want to form busses of the "columns" for lack of better terms. I can do it the long way:

   assign col31 = {row31[31], row30[31], ... row1[31], row0[31]} ;

但是要打很多字.有没有更简单的方法?

but it's a lot of typing. Is there an easier way?

推荐答案

在 Verilog 中没有简单的方法.尝试创建一个脚本来为您生成代码.您可以使用首选编程语言生成代码，然后在 verilog 文件中使用 `include 语句.或者您可以使用嵌入式路由:

There is no easy way within Verilog. Try creating a script to generate the code for you. You can have the code generated by your preferred programming language, then use an `include statement in your verilog file. Or you can go with an embedded route:

• Perl 有 EP3:http://metacpan.org/pod/Text::EP3:: Verilog
• Ruby 有 eRuby:http://www.tutorialspoint.com/ruby/eruby.htm
• Python 有 prepro :http://corner-case.com/indproj/prepro.html
• 我相信其他语言也有类似的东西.如 Tcl、JavaScript、C 等.

概念相同，只是嵌入语言和转换工具不同.

Concept is the same, just a difference in embedded language and tool used for conversion.

在这种情况下，将需要如下所示的双循环:

In this case, a double for-loop like the following will be needed:

foreach my $i (0..31) {
  foreach my $j (0..31) {
    printf("assign col%0d[%0d] = row%0d[%0d];\n", $i,$j, $j, $i);
  }
}

<小时>

使用SystemVerilog，您可以使用阵列输入/输出端口重新定义您的模块.实例化时可能会增加难度，我尝试使用合成器将数组展平.但它可以工作.Verilog 不支持这个，SystemVerilog 支持.

---

With SystemVerilog you could redefine your module with arrayed input/output ports. It may add difficulty when instantiating, and a synthesizer my attempt flatten the array. But it could work. Verilog does not support this, SystemVerilog does.

module row2col #(parameter WIDTH=32) (
    input wire [WIDTH-1:0] row [WIDTH],
    output logic [WIDTH-1:0] col [WIDTH]
  );
  always_comb begin
    foreach(row[i,j]) begin
      col[j][i] = row[i][j];
    end
  end
endmodule : row2col

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