如何在verilog中使用环境变量或命令行设置宏的值? [英] How to set the value of a macro using environment variable or command line in verilog?
问题描述
我想在运行时使用环境变量在 Verilog 中定义一个宏.
I want to define a macro during runtime in Verilog using environment variable.
例如,我想仅在 DEBUG
宏定义为 1
时才将一些文本打印到文件中.
For example, I want to print some text to a file only when the DEBUG
macro is defined as 1
.
`define DEBUG 0
...
if(DEBUG) $fwrite(file,"Debug message");
从命令行运行模拟或使用环境变量时,如何将 DEBUG
的定义覆盖为 1
?
How can I override the definition of DEBUG
to 1
when running the simulation from command line or using environment variable?
或者,我可以保持宏未定义并使用 ifdef
Alternatively, I could keep the macro undefined and use ifdef
`ifdef(DEBUG) $fwrite(file,"Debug message");
在这种情况下,我必须在运行模拟时定义宏 DEBUG
.这可能吗?
In this case I would have to define the macro DEBUG
when running the simulation. Is this possible?
我正在使用 Modelsim.谢谢.
I am using Modelsim. Thanks.
EDIT:接受的答案就足够了.但我也会为在这里偶然发现的任何人添加这些信息.
EDIT: The accepted answer is sufficient. But I will add this information too for anyone who stumbles upon here.
可以使用 -g
或 -G
参数来设置/覆盖参数的值 vsim
.-g
仅在尚未设置的情况下设置参数值,并且 -G
设置该值即使已定义.当我使用参数控制模拟长度时,我发现这很方便.不需要重新编译.
The value of a parameter can be set/overriden by using -g<parameter>
or -G<parameter>
argument to vsim
. -g
sets the parameter value only if it hasn't been set already and -G
set the value even if it's defined. I found this convenient when I control simulation length using parameter. Recompilation isn't necessary.
vsim -c work.top -gSIM_END_TIME // Sets value in all scope
vsim -c work.top -g/top/dut/SIM_END_TIME // Sets value only in the defined scope
推荐答案
您可以使用 vlog 命令行选项 +define+<macro_name>[=<macro_text>]
You can override a macro definition with the vlog command line option +define+<macro_name>[=<macro_text>]
更好的选择是不定义宏并使用 `ifdef
语句来测试您是否在命令行上定义了它.
The better option is to leave the macro undefined and use the `ifdef
statement to test if you have defined it on the command line.
请注意,使用宏需要在每次要更改宏值时重新编译源代码.Verilog 提供了 $test$plusargs
和 $value$plusargs
来在运行时测试命令行选项,因此您不需要重新编译.
Note that using a macro requires you to recompile your source code every time you want to change the macro value. Verilog provides $test$plusargs
and $value$plusargs
to test command line options at runtime so you do not need to recompile.
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