Verilog 4 位加减计数器使用负边沿触发 T 触发器设计 [英] Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

问题描述

我对 Verilog HDL 非常陌生，我必须编写这个 4 位递增递减计数器.借助对加减计数器和 t 触发器的一些阅读，我已经编写了以下代码:

I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code:

module up_down_4bitcounter (
out,
up_down,
clk,
data,
reset
);

//Output Ports
output [3:0] out;

//Input Ports
input [3:0] data;
input up_down, clk, reset;

//Internal Variables
reg [3:0] out;

//Start of Code
always @(negedge clk)
if (reset) begin // active high reset
out <= 4'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end

endmodule 

现在，我收到此错误:

Exercise5_1.v:25: syntax error
Exercise5_1.v:25: error: unmatched character (')
Exercise5_1.v:25: error: malformed statement

第 25 行是这样的:

Line 25 is this one:

out <= 4'b0 ;

我不是 100% 确定我的编码是否正确.你能告诉我我的问题在哪里吗?

I am not 100% sure if my coding is correct. Can you tell me where my issue is?

推荐答案

Line 25 is this one:

第 25 行有错误:

out <= 4'b0 ;

答案是:

Out <= 4'b0000 ;

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