为什么我总是在 Verilog 代码中出现语法错误? [英] Why do I get Syntax error near always in Verilog code?

问题描述

我正在尝试运行此代码，但出现以下错误:

I am trying to run this code, and it is giving these errors:

Syntax error near "always"
Syntax error near "endmodule"

我不明白这段代码有什么问题:

I don't understand what is wrong in this code:

module fortran_v2(
    input clk
    );
parameter N=8;
parameter M=6;
parameter size=1000;     
reg [N-1:0] A [0:size-1];
reg [N-1:0] B [0:size-1];
reg [M-1:0] C [0:size-1];
reg [M-1:0] D [0:size-1];
reg [15:0] k=0;
integer open_file;
initial begin
open_file= $fopen("output.txt","w");
end

always @ (posedge clk) begin
if(k<1000)
k<=k+1;
else
k<=1000;
end

always @ (posedge clk) begin
if(k<1000) begin
  A[k]<=$random;
  B[k]<=$random;
  end

always @ (posedge clk) begin
if (k<1000) begin
  C[k]<=A[k]*B[k] +5;
  D[k]<=A[k]+B[k] -5;
  $fwrite(open_file,"A[%d",k,"]",A[k],"B[%d",k,"]",B[k],"C[%d",k,"]",C[k],"D[%d",k,"]",D[k]);
end
else
  A[k]=0;
end  
endmodule

推荐答案

如果使用适当的缩进，就没有问题.在您的 always 块之一中，缺少关键字 end:

You'd have no problem if you use a proper indentation. In one of your always blocks, keyword end is missing:

always @ (posedge clk) begin
  if(k<1000) begin
    A[k]<=$random;
    B[k]<=$random;
  end
end //missing end

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