VHDL实体和架构设计 [英] VHDL entity and architecture design

问题描述

使用 Ada，我可以使用 .ads 和 .adb 文件将我的模块化单元拆分为规范和正文.

With Ada I can split my modular units into specification and body with .ads and .adb files.

是否可以分离 VHDL 实体和架构?如果是这样，是否有命名约定或推荐的样式来执行此操作?实体可以放在自定义库/包中吗?

Is it possible to separate VHDL entity and architecture? If so, is there a naming convention or recommended style for doing this? And can the entities be placed in a custom library/package?

推荐答案

图书馆

一切都被编译成一个库.默认情况下，这称为工作"，但您可以覆盖它.不过，我很少需要使用它 - 如果存在命名空间冲突，它偶尔会对外部 IP 有用.正如 Chiggs 评论的那样，使用库来创建命名空间是一种很好的做法.大多数合成器现在可以处理多个库，尽管情况并非总是如此.所有模拟器都可以(据我所知).设置它们也有点麻烦(你必须告诉编译器它们都在哪里).

Libraries

Everything gets compiled into a library. By default this is called "work", but you can override this. I rarely have to use that though - it's occasionally useful with external IP if there are namespace clashes. As Chiggs commented, using libraries to create namespaces is a good practice. Most synthesizers can deal with multiple libraries now, although it wasn't always the case. All the simulators can (as far as I know). There's also a bit more hassle involved in setting them up (you have to tell the compiler where they all are).

也许是一个例子 - 假设你有一个 i2c 控制器和一个 spi 控制器.你可以调用两个块 controller 并将它们编译成它们自己的名为 i2c 和 spi 的库，然后像这样实例化它们:

maybe an example - say you have an i2c controller and an spi controller. You could call both blocks controller and compile them into their own libraries called i2c and spi and then instantiate them like this:

i2c_instance:entity i2c.controller...etc
spi_instance:entity spi.controller...etc

或者你可以称它们为 i2c_controller 和 spi_controller 并执行:

or you could call them i2c_controller and spi_controller and do:

i2c_instance:entity work.i2c_controller...etc
spi_instance:entity work.spi_controller...etc

<小时>

而且库与硬盘文件夹并不完全相同".它们由 VHDL 编译器管理，因此您可以使用工具使用的任何语法来创建和映射它们.

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And libraries are not "just the same" as hard disk folders. They are managed by the VHDL compiler, so you create and map them using whatever syntax the tool uses.

例如对于 Modelsim，vlib 在文件系统的特定位置创建一个库(所以它看起来像一个文件夹)并且 vmap 告诉编译器如何将 use some_lib; 子句映射到文件系统的特定位.

For example with Modelsim, vlib creates a library at a particular place in the filesystem (so it does look like a folder at this point) and vmap tells the compiler how to map a use some_lib; clause to a particular bit of the filesystem.

您可以将实体和架构(甚至每个实体一个以上的架构)分离到多个文件中，或者将它们保存在一个文件中.将 architecture 保存在单独的文件中意味着当您重新编译它时，您无需重新编译 entity，这意味着您不必重新编译实例化它的所有内容.

You can separate your entity and architecture (or even more than one architecture per entity) into multiple files, or keep them in one file. Keeping the architecture in a separate file means that when you recompile it, you don't recompile the entity, which means you don't have to recompile everything that instantiates it.

与 packages 和 package bodys 类似 - 在单独的文件中的主体意味着您可以重新编译该部分而无需重新编译其他所有内容.请注意，packages 不是用来放入实体的.

Similarly with packages and package bodys - bodies in a separate file means you can just recompile that part without recompiling everything else. Note that packages are not for putting entities in.

(另外 - Modelsim 有一个 -just 开关，它允许您将所有内容保存在一个文件中，并且只编译文件的选定部分，例如，仅编译 架构和/或 body 部分)

(Aside - Modelsim has a -just switch that allows you to keep everything in one file and just compile selected bits of the files, for example, just the architecture and/or body part(s))

• 将可重复使用的内核编译到他们自己的库中以保护他们的命名空间
• 将其他所有内容编译到 work 库中
• 将有用的常量、函数、过程、类型定义放入一个或多个包中
• 将实体和架构放入一个或多个文件中比其他任何事情都更取决于品味和开发风格
• 将包和包主体放入一个或多个文件中比其他任何事情都更取决于品味和开发风格

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