VHDL中行为和数据流模型程序之间的混淆 [英] Confusion between Behavioural and Dataflow model Programs in VHDL

问题描述

我正在使用 Douglas L Perry 的教科书VHDL:Programming By Example"，第四版.他在第 4 页中给出了 Dataflow 编程模型的示例:

I'm using the textbook "VHDL: Programming By Example" by Douglas L Perry, Fourth Edition. He gave an example of the Dataflow programming model in page 4:

代码一:

ENTITY mux IS
PORT ( a, b, c, d : IN BIT;
s0, s1 : IN BIT;
x, : OUT BIT);
END mux;
ARCHITECTURE dataflow OF mux IS
SIGNAL select : INTEGER;
BEGIN
select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE
          1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE
          2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE
          3;
x <= a AFTER 0.5 NS WHEN select = 0 ELSE
     b AFTER 0.5 NS WHEN select = 1 ELSE
     c AFTER 0.5 NS WHEN select = 2 ELSE
     d AFTER 0.5 NS;
END dataflow;

现在在第 17 页，代码二

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT ( i0, i1, i2, i3, a, b : IN std_logic;
PORT ( i0, i1, i2, i3, a, q : OUT std_logic);
END mux4;
ARCHITECTURE mux4 OF mux4 IS
SIGNAL sel: INTEGER;
BEGIN
WITH sel SELECT
q <= i0 AFTER 10 ns WHEN 0,
q <= i1 AFTER 10 ns WHEN 1,
q <= i2 AFTER 10 ns WHEN 2,
q <= i3 AFTER 10 ns WHEN 3,
q <= ‘X’ AFTER 10 ns WHEN OTHERS;
sel <= 0 WHEN a = ‘0’ AND b = ‘0’ ELSE
       1 WHEN a = ‘1’ AND b = ‘0’ ELSE
       2 WHEN a = ‘0’ AND b = ‘1’ ELSE
       3 WHEN a = ‘1’ AND b = ‘1’ ELSE
       4;
END mux4;

根据同一教科书，这应该是一个行为模型.除了变量名的不同，我在这里看到的唯一主要区别是有一个额外的声明

This is supposed to be a behavioural model, as per the same textbook. Aside from the differences in variable name, the only major difference I see here is that there is an extra statement

WITH sel SELECT

在第二种情况下，语法差异很小.此代码 II 是并发的.但是从互联网上的其他来源(如下所列)，我已经看到行为模型应该是顺序的.我应该相信哪一个?

in the second case, and small syntax differences. This Code II is concurrent. But from other sources in the internet(listed below), I've seen that a behavioural model is supposed to be sequential. Which one should I believe?

现在从互联网的一些其他来源，这些模型的定义如下:

Now from some other sources of the internet, the definition of these models are as follows:

行为 - 电路被描述为使用 进程内的顺序语句的 i/o 关系.

Behavioral – Circuit is described as an i/o relationship using sequential statements inside a process.

数据流 - 使用并发语句描述电路

Dataflow – Circuit is described using concurrent statements

-圣何塞州立大学

行为 - 描述如何使用结构化从输入中导出输出声明.

Behavioral – describes how the output is derived from the inputs using structured statements.

数据流 – 描述数据如何流动.

Dataflow – describes how the data flows.

-阿克伦大学工程学院

在行为层面，存在process关键字

in Behaviour level, process keyword is present

在数据流级别，存在并发语句 (<=)

in dataflow level , concurrent statement (<=) is present

这是在一个在线论坛上看到的.

This was seen in an online forum.

行为模型是否必须使用流程声明?

Is process statement compulsory for Behavioural model?

代码 I 和 II 之间的实际区别是什么?据作者介绍，它们有不同的模型、数据流和行为.我看不出这是怎么可能的.我应该相信什么?

What is the actual difference between codes I and II? According to the author, they have different models, dataflow and behavioural. I cannot see how this is possible. What should I believe?

最后，在 Perry D L，第 45、46 页:

Lastly, in Perry D L, Page 45, 46:

LIBRARY IEEE;
USE IEEE.std_logic_1164ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN std_logic;
PORT (q : OUT std_logic);
END mux;
ARCHITECTURE better OF mux IS
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
VARIABLE muxval : INTEGER;
BEGIN
muxval := 0;
IF (a = ‘1’) THEN
muxval := muxval + 1;
END IF;
IF (b = ‘1’) THEN
muxval := muxval + 2;
END IF;
CASE muxval IS
WHEN 0 =>
q <= I0 AFTER 10 ns;
WHEN 1 =>
q <= I1 AFTER 10 ns;
WHEN 2 =>
q <= I2 AFTER 10 ns;
WHEN 3 =>
q <= I3 AFTER 10 ns;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END better;

这是 MUX 的顺序版本.根据其他定义，这应该是行为，但作者没有说明.你能澄清我对这些模型的困惑吗?

This is a sequential version of MUX. According to the other definitions, this is supposed to be behavioural, but the author does not state so. Could you clear up my confusion regarding these models?

推荐答案

不要寻找这些术语的数学上严格的描述；它们比这要模糊得多，松散的分类可以重叠.

Don't look for a mathematically rigorous description of these terms; they are a lot vaguer than that, loose classifications that can overlap.

数据流"我认为这里很清楚；它确实描述了数据流，并根据并发语句进行了描述.但我要补充的是，每个并发语句都被其输入的变化唤醒并提供其输出；因此(重要的一点:)事情发生的顺序和源代码中元素的顺序之间没有对应关系.在这方面，它与函数式编程有很多共同点.前两个模型都是数据流；(I) 中的元素是按逻辑顺序排列的，而 (II) 则不是.

"Dataflow" I think is fairly clear here; it DOES describe the flow of data, and it describes it in terms of concurrent statements. But I would add that each concurrent statement is woken by changes on its inputs and delivers its outputs; therefore (the important bit:) there is no correspondence between the order of things happening and the order of elements in the source code. In that respect it has a lot in common with functional programming. And both the first two models are dataflow; in (I) the elements are in logical order while (II) is not.

行为"也应该相当清楚——它只是根据行为描述了一个电路.

"Behavioural" SHOULD be fairly clear too - it simply describes a circuit in terms of its behaviour.

但它通常并不反对数据流——尽管你的圣何塞引用有些正确——行为描述通常只是因为顺序范式(在 VHDL 中)过程)对程序员来说是常见和熟悉的.即便如此，相互交互的几个这样的进程的行为是......数据流.

But it is not in general opposed to dataflow - though your San Jose quote is somewhat correct - behavioural descriptions are commonly sequential simply because the sequential paradigm (inside a VHDL process) is common and familiar to programmers. Even so, the behaviour of several such processes interacting with each other is ... dataflow.

行为与数据流并不完全相反.它更正确地反对 RTL(注册传输级别)和 结构，它们具有相当明确的含义.

Behavioral then is NOT correctly opposed to dataflow. It is more correctly opposed to RTL (Register Transfer Level) and structural which have fairly clear meanings.

结构描述由许多构建块(门、多路复用器、整个 CPU)和互连它们的信号组成:文本框图(可能从图形框图自动生成).因此，它可以是最低级别(请参阅此处关于使用门制作加法器的常见问题！)或最高级别(将 CPU 连接到内存、外设等).

A structural description consists of a number of building block (gates, multiplexers, entire CPUs) and the signals interconnecting them : a textual block diagram (perhaps auto-generated from a graphical one). As such it can be either the lowest level (see frequent questions here about making an adder out of gates!) or the highest level (connecting CPU to memory, peripherals, etc).

RTL 描述相当低级；它描述了存储元素(寄存器)之间的数据传输和操作，在进程内部很常见；它更像是来自(行为)C 程序的汇编语言列表.

An RTL description is fairly low level; it describes the transfer and operations on data between storage elements (registers) and is common inside a process; it is rather like an assembly language listing from a (behavioural) C program.

最后 - 过多的描述和过多的无关细节妨碍了正确的设计工作.查看手头的任务，提取其本质，然后实施.

Lastly - too many descriptions and too many extraneous details get in the way of doing a proper design job. Look at the task in hand, extract its essence, and implement that.

多路复用器根据您想要的元素的索引选择一组输入元素中的一个.最自然的索引形式通常是整数类型，很少包括负索引，而 VHDL 中最自然的集合形式是……数组.

A multiplexer selects one of a collection of input elements according to the index of the element you want. The most natural form of index is usually an integer type, rarely including negative indices, and the most natural form of collection in VHDL is ... an array.

为什么不写

ENTITY mux IS
  PORT ( a, b, c, d : in BIT;
         sel        : in natural range 0 to 3;
         x          : out BIT);
END mux;
ARCHITECTURE simple OF mux IS
SIGNAL values : array (0 to 3) of BIT;
BEGIN
   values <= a & b & c & d;
   x      <= values(sel);   -- after 0.5 ns; if you need to model timing!
END simple;

或者更好，使值"成为输入端口...

or better, make "values" an input port...

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