VHDL - 为什么直接在函数上使用长度属性会产生警告? [英] VHDL - Why does using the length attribute directly on a function produce a warning?

问题描述

我有一个 VHDL 函数，它返回一个记录的 std_logic_vector 表示，我想要该 std_logic_vector 的长度.我可以直接在函数上使用 length 属性.为什么这会在 ModelSim 中产生警告?我在邀请微妙的问题吗?谷歌搜索警告文本没有发现任何我认为有帮助的内容.

my_function_returns_slv(my_record)'length;

<块引用>

** 警告:../src/my.vhd(line#): (vcom-1515) 预定义属性长度"的前缀是函数调用my_function_returns_slv"

我编写了通过连接记录元素的 std_logic_vector 表示来组装输出的函数.记录的长度在编译时是固定的，但我不想对长度进行硬编码.我需要长度来创建使用函数输出的信号.所以我不能只在函数的输出上调用 'length (例如:在保存函数输出的信号上调用 'length)，因为不可能声明一个不受约束的信号来保存输出.我可以编写一个类似的函数来计算 std_logic_vector 的长度，但这会增加一些重要的代码，尤其是对于我拥有的记录数.我应该接受 ModelSim 警告并继续吗?我应该处理编写函数的额外代码来组装我的记录的位宽吗?有没有更好的解决方案?

我正在使用的有用的记录打包/解包子程序:

http://www.eda-twiki.org/twiki/pub/P1076/RecordReflectionToSlv/standard_functions.vhd

谢谢！

解决方案

直接在函数上使用 'length 属性可以被看作只是取了函数结果的另一部分而不是主要输出，因此，从概念的角度来看，这应该没有错.

所以我会接受 ModelSim 警告，但也将其视为该工具担心构造的迹象，因此我会检查我的其他工具，例如综合工具和代码检查器，直接在函数调用上接受属性的这种使用.

看起来您可以通过创建如下函数来避免 ModelSim 警告:

function len(slv : std_logic_vector) return natural is开始返回slv'长度；结束函数；

然后这不会导致 ModelSim 警告:

信号 MY_LEN : natural := len(slv_not(CONST));

因此能够使用这种封装来避免警告首先证实警告有点不稳定.

I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why does this produce a warning in ModelSim? Am I inviting subtle problems? Googling the warning text did not turn up anything I understood to be helpful.

my_function_returns_slv(my_record)'length;

** Warning: ../src/my.vhd(line#): (vcom-1515) Prefix of predefined attribute "length" is function call "my_function_returns_slv"

I've written the function to assemble the output by concatenating std_logic_vector representations of the record elements. The length of the record is fixed at compile time, but I do not want to hard code the length. I need the length to create signals for using the function output. So I can't just call 'length on the output of the function (ex: call 'length on a signal holding the function output) because it is not possible to declare an unconstrained signal to hold the output. I could write a similar function to calculate the length of the std_logic_vector, but that would add some significant code, especially for the number of records I have. Should I accept the ModelSim warning and carry on? Should I deal with the extra code from writing functions to assemble the bit width of my records? Is there a better solution altogether?

Helpful record pack/unpack subprograms I am making use of:

http://www.eda-twiki.org/twiki/pub/P1076/RecordReflectionToSlv/standard_functions.vhd

Thanks!

解决方案

Using the 'length attribute directly on a function can be seen as just taking another part of the function result than the primary output, thus from a conceptual point of view there should be nothing wrong with that.

So I would accept the ModelSim warning, but also take it as an indication that the tool is worried about the construction, so I would check that my other tools, e.g. synthesis tools and code checkers, accept this use of an attribute directly on a function call.

Appears that you can avoid the ModelSim warning by making a function like:

function len(slv : std_logic_vector) return natural is
begin
  return slv'length;
end function;

and then this won't result in a ModelSim warning:

signal MY_LEN : natural := len(slv_not(CONST));

So being able to avoid the warning using such encapsulation confirms that the warning is a little flaky in the first place.

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