组件声明有什么用处? [英] What is the usefulness of a component declaration?

问题描述

随着 VHDL '93 引入直接实例化，当您的实体在 VHDL 中时，您现在何时真正使用组件?以下是我能想到的唯一需要组件的时间:

With VHDL '93 introducing direct instantiation, when would you actually use a component now when your entity is in VHDL? The following are the only time when a component is required I can think of:

1. 组件映射到非 VHDL 源(Verilog、网表等)
2. 你还没有源代码，需要一些东西来编译(例如，同事还没有完成他们的代码)
3. 您正在通过配置将不同的实体/架构对绑定到特定实体中的特定组件.(但谁真正做到了这一点?也许如果你有一个模拟拱门和合成拱门 - 但同样 - 从未见过它以任何有意义的方式使用)

我对那些说一个组件让我在同一个文件中看到端口映射"的人不屑一顾.或拥有组件库可以让我看到一切".这主要是人们已经习惯的老派方法.在我看来，在两个地方维护相同的代码是没有意义的.

I am discounting people who say that "A component lets me see the port map in the same file" or "having a component library allows me to see everything". This is mostly an old-school approach that people have got into the habit of. In my eyes, maintaining the same code in two places makes no sense.

还有其他我想念的吗?

推荐答案

抱歉迟到了 无法编译 VHDL 包 - Modelsim 错误:(vcom-1576) 期待结束

除了 OP 列出的用例并符合他的不那么有用的用例标准，我将添加另外两个用例:

In addition to the use case listed by the OP and in compliance with his criteria of not so useful cases, I'll add two more cases:

1. 要编写独立于平台的代码，需要实现例如Altera 和 Xilinx 特定解决方案.此代码将引用供应商特定的库，例如 alter_mf 或 unisim.可以通过 if ... generate-statement 或从 VHDL-2008 开始通过 case ... generate-statement 选择这两种特定于供应商的实现.
   但即使使用 generate 语句，该解决方案也需要实例化组件，因为直接实体实例化的实例是绑定的，而不管某些实例永远不会出现在详细模型中的事实.(我认为这是语言中的一个错误 - 但没有时间针对 VHDL-2018 进行调查和修复.)因为实体立即绑定，该工具会尝试加载引用的供应商库及其包.
   假设您使用 Quartus 在 Altera 上编译，它会抱怨未知的 unisim 库和未知的 vcomponents 包.在 Xilinx 上也会发生同样的情况，Vivado 抱怨一个未知的 altera_mf 库.
   因此，为了切断(直接)实例化树，需要一个组件实例化.

1. To write platform independent code, one needs to implement e.g. an Altera and a Xilinx specific solution. This code will reference vendor specific libraries like alter_mf or unisim. Both vendor specific implementations can be selected by a if ... generate-statement, or since VHDL-2008 by a case ... generate-statement.
   But even with generate-statements, this solution needs to instantiate components, because instances of a direct entity instantiation are bound regardless of the fact that some instances will never appear in the elaborated model. (I consider this a bug in the language - but there was no time to investigate and fix it for VHDL-2018.) Because an entity is immediately bound, the tool tries to load the referenced vendor library and it's packages.
   Let's assume you compile on Altera with Quartus, it will complain about an unknown unisim library and a unknown vcomponents package. The same happens on Xilinx with Vivado complaining about an unknown altera_mf library.
   Thus, to cut-off the (direct) instantiation tree, a component instantiation is needed.

此技术由 PoC-Library 使用.例如参见 PoC.misc.sync.Bits 标准双 FF 同步器的实现，具有应用于 Altera、Xilinx 或通用实现的不同属性.

This technique is used by the PoC-Library. See for example the PoC.misc.sync.Bits implementation for a standard double-FF synchronizer with different attributes applied to an Altera, Xilinx or generic implementation.

在开源VHDL验证方法(OSVVM)中，组件用于两个用例:

In the Open Source VHDL Verification Methodology (OSVVM), components are used for two use cases:

1. 在顶层 DUT 中，IP 核被实例化为组件，因此它们可以被虚拟实现替换.作为未绑定的组件或作为加载虚拟架构的组件.这可以加快模拟速度，减少测试中可能的错误源，用更简单、更快速的实现替换 MGT 或内存控制器等复杂的缓慢实现，......
2. 在 OSVVM 中，测试控件在名为 TestController 的单独实体中实现.该实体有多种架构来实现应用于相同测试硬度的不同测试用例.体系结构与每个测试用例/体系结构的顶级配置绑定.因此，运行测试平台"意味着精心设计和模拟这些配置之一.

1. In a toplevel DUT, IP cores are instantiated as components so they can be replaced by dummy implementations. Either as unbound components or as components loading a dummy architecture. This can speed up simulations, reduce possible error sources in testing, replace complex slow implementations like MGTs or memory controllers with simpler and faster implementations, ...
2. In OSVVM, the test control is implemented in a separate entity called TestController. This entity has several architectures to implement the different test cases applied to the same test hardness. The architectures are bound with a toplevel configuration per test case / architecture. Thus, running a "testbench" means elaborating and simulating one of these configurations.

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