在多个进程中分配信号 [英] Assign signal in many processes

问题描述

我尝试学习VHDL语言我不明白一件奇怪的事情.这个东西指的是来自架构的信号.

I try to learn VHDL language I don't understand a strange thing. This thing refers to the signals from an architecture.

我的问题是:为什么我们不能在多个进程/并发分配中分配位信号、整数信号等.但是我看到了，我们可以在多个进程中分配Std_logic_vector信号和Std_logic信号.

My question is: Why we can't assign bit signal, integer signal, etc in more than one process/ concurrent assign. But I saw, we can assign in more than one process Std_logic_vector signal and Std_logic signal.

推荐答案

如果在详细描述之后，一个信号是错误的有多个来源，它不是一个已解析的信号.

It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal.

IEEE Std 1076-2008 6.4.2.3 信号声明.

IEEE Std 1076-2008 6.4.2.3 Signal declarations.

与解析信号相关的解析函数决定了信号的解析值作为集合的函数来自多个来源的输入.

The resolution function associated with a resolved signal determines the resolved value of the signal as a function of the collection of inputs from its multiple sources.

4.6 解析函数.

std_logic 或 std_logic_vector(命名为已解析)的解析函数可在 std_logic_1164 包体中找到.

The resolution function for std_logic or std_logic_vector (named resolved) is found in the std_logic_1164 package body.

对多个驱动程序的限制可以是由综合工具限制和定义的目标设备.

Restrictions on multiple drivers can be target device limited and defined by synthesis tools.

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