超出非静态循环限制 [英] Non-static loop limit exceeded

问题描述

我想实现 K&R 算法来计算 256 位向量的汉明权重.我在 vhdl 中编写了我的代码:

I want to implement the K&R algorithm for hamming weight calculation of 256 bit vector. I have written my code in vhdl as:

entity counter_loop is
    Port ( dataIn : in  STD_LOGIC_VECTOR (255 downto 0);
              dataOut : out STD_LOGIC_VECTOR (8 downto 0);
           threshold : in  STD_LOGIC_VECTOR (8 downto 0);
           clk : in  STD_LOGIC;
           flag : out  STD_LOGIC);
end counter_loop;

architecture Behavioral of counter_loop is
    signal val : STD_LOGIC_VECTOR (255 downto 0) := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
begin
    process (clk)
        variable count : STD_LOGIC_VECTOR (8 downto 0):= "000000000";       
    begin
        flag <= '0';
        val <= dataIn;
        --if(clk'event and clk = '1') then 
            while (val > 0) loop
                count := count+1;
                val <= (val and (val-1));
                if (count > threshold) then
                    flag <= '1';
                end if;
            end loop;
                dataOut <= count;
        --end if;
    end process;
end Behavioral;

但是，在使用 Xilinx 对其进行综合时，错误显示为

But, while synthesizing it using Xilinx, the error comes up as

第 53 行:超出非静态循环限制

Line 53: Non-static loop limit exceeded

请问有什么线索吗?

P.S:第 53 行是 - while (val > 0) 循环

P.S: Line 53 is - while (val > 0) loop

推荐答案

所以，我将忽略实际满足时间的事情的问题(val - 1 很昂贵)并实际谈谈你的逻辑.

So, I'm going to ignore issues of things actually meeting timing (val - 1 is expensive) and actually talk about your logic.

这是您的一段代码:

signal val : std_logic_vector(255 downto 0) := (others => '1');

process (clk)
begin
    while (val > 0) loop
        val <= (val and (val-1));
    end loop;
end process;

val 是一个信号，而不是一个变量.这意味着它将在您完成增量周期时更新.在这种情况下，永远不会.所以你有一个无限循环.

val is a signal, not a variable. That means it will be updated when you finish the delta cycle. Which in this case, will be never. So you have an infinite loop.

如果您只是想计算一个数字的 popcount，那么为什么不这样做呢?虽然我怀疑这也能满足时序要求(可能需要在多个时钟周期内分解它).

If you're just trying to calculate the popcount of a number, then why don't you just do this. Although I doubt this will meet timing as well (Probably need to break it up over multiple clock cycles).

process (clk)
    variable count : std_logic_vector(8 downto 0) := "0" & x"00";
begin
    if rising_edge(clk) then
        for i in dataIn'range loop
            if dataIn(i) = '1' then
                count := count + 1;
            end if;
        end loop;

        dataOut <= count_i;
    end if;
end process;

<小时>

最后，大多数人会争辩说，为 C 代码设计的算法通常在硬件上表现不佳，因为硬件与固定处理器的功能不同.

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And finally, most people would argue that algorithms designed for C code often perform poorly in hardware, because hardware has different capabilities than a fixed processor.

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