在 VHDL 中实现计数器 [英] Implementing a counter in VHDL

问题描述

以下代码实现了一个两位数的计数器并在七个段上显示输出.可以看出，在每个时钟周期中，该值都必须改变，但仿真结果并没有显示出这样的事情.为了减少代码量，我在七段驱动中只放了0和1.

The following code implements a two digit counter and displays the output on seven segments. As can be seen, in each clock cycle, the value has to be changed but the simulation results doesn't show such thing. To reduce the code size, I only put 0 and 1 in the seven segment driver.

library ieee;
use ieee.std_logic_1164.all;

entity two_digit_counter is
    port( clk: in std_logic;
          x, y: out std_logic_vector( 6 downto 0 ));
end;

architecture x of two_digit_counter is
begin
    process( clk )
        variable d1 : integer range 0 to 9 := 0;
        variable d2 : integer range 0 to 9 := 0;
    begin
        if (clk'event and clk = '1') then
            if d1 = 9 then
                d1 := 0;
                d2 := d2 + 1;
            elsif d2 = 9 then
                d2 := 0;
                d1 := 0;
            else
                d1 := d1 + 1;
            end if;
        end if;

        case d1 is
            when 0   =>    x <= "1111110";  -- 7E
            when 1   =>    x <= "0110000";  -- 30
        end case;
        case d2 is
            when 0   =>    x <= "1111110";
            when 1   =>    x <= "0110000";
        end case;
    end process;
end;

推荐答案

很遗憾，除了缺少对 y 的赋值之外，您的 d2 计数器无法正常工作:

Unfortunately your d2 counter doesn't work properly besides the missing assignments to y:

d2 底部跟踪应保留 d1 的 10 个计数的每个值(此处显示为 10 秒.if 语句不全面，应该更改.d1 也显示不正确.

d2 the bottom trace should hold each value for 10 counts of d1 (here shown as ten seconds. The if statements aren't comprehensive and should be changed. d1 is showing up incorrectly as well.

通过嵌套两个计数器 if 语句来解决这个问题:

Fix that by nesting the two counter if statements:

    process (clk)
        variable d1 : integer range 0 to 9 := 0;
        variable d2 : integer range 0 to 9 := 0;
    begin
        if rising_edge(clk) then
            -- if d1 = 9 then
            --     d1 := 0;
            --     d2 := d2 + 1;
            -- elsif d2 = 9 then
            --     d2 := 0;
            --     d1 := 0;
            -- else
            --     d1 := d1 + 1;
            -- end if;
            if d1 = 9 then       -- nested if statements
                d1 := 0;
                if d2 = 9 then
                    d2 := 0;
                else
                    d2 := d2 + 1;
                end if;
            else
                d1 := d1 + 1;
            end if;
        end if; 
        case d1 is
            when 0   =>    x <= "1111110";  -- 7E
            when 1   =>    x <= "0110000";  -- 30
            when 2   =>    x <= "1101101";  -- 6D
            when 3   =>    x <= "1111001";  -- 79
            when 4   =>    x <= "0110011";  -- 33
            when 5   =>    x <= "1011011";  -- 5B
            when 6   =>    x <= "1011111";  -- 5F
            when 7   =>    x <= "1110000";  -- 70
            when 8   =>    x <= "1111111";  -- 7F
            when 9   =>    x <= "1111011";  -- 7B
        end case;
        case d2 is
            when 0   =>    y <= "1111110";   -- WAS assignment to x
            when 1   =>    y <= "0110000";   -- ""
            when 2   =>    y <= "1101101";
            when 3   =>    y <= "1111001";
            when 4   =>    y <= "0110011";
            when 5   =>    y <= "1011011";
            when 6   =>    y <= "1011111";
            when 7   =>    y <= "1110000";
            when 8   =>    y <= "1111111";
            when 9   =>    y <= "1111011";
        end case;
    end process;

这会产生:

如果您的问题提供了最小、完整和可验证的示例，则您的问题的其他答案可能会指出这一点.

Your question's other answers could have pointed this out if your question had provided a Minimal, Complete and Verifiable example.

这篇关于在 VHDL 中实现计数器的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！