VHDL 错误无法推断寄存器，因为其行为与任何支持的寄存器模型都不匹配 [英] VHDL error can't infer register because its behavior does not match any supported register model
问题描述
我是 VHDL 的新手，正在尝试为可编程 FPGA 制作延迟/门应用程序，延迟和门输出的长度可调.一旦接收到输入信号，事物就应该忽略任何其他输入，直到门信号的生成完成.
I am new to VHDL and trying to make a delay/gate application for programmable FPGA, with adjustable lenght of delay and gate output. As soon as the input signal is recieved, the thing should ignore any other inputs, until generating of gate signal is finished.
我想稍后将此组件用于 8 个不同的输入和 8 个不同的输出，并通过写入寄存器的方式分别为每个设置所需的延迟/门参数.
I want to use this component for 8 different inputs and 8 different outputs later, and set desired delay/gate prameters separately for each one by means of writing registers.
尝试在 Quartus II v 11.0 中编译时出现此错误:
When trying to compile in Quartus II v 11.0 i am getting this error:
错误 (10821):clkgen.vhd(46) 中的 HDL 错误:无法推断control_clkgen"的寄存器，因为其行为与任何支持的寄存器模型不匹配
Error (10821): HDL error at clkgen.vhd(46): can't infer register for "control_clkgen" because its behavior does not match any supported register model
还有
错误 (10822):clkgen.vhd(37) 上的 HDL 错误:无法在此时钟沿上实现用于分配的寄存器
Error (10822): HDL error at clkgen.vhd(37): couldn't implement registers for assignments on this clock edge
不知道怎么了，这里是组件的代码:
No idea whats wrong, here is the code of the component:
library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;
ENTITY clkgen is
port(
lclk : in std_logic;
start_clkgen : in std_logic;
gate_clkgen : in std_logic_vector(31 downto 0);
delay_clkgen : in std_logic_vector(31 downto 0);
output_clkgen : out std_logic
);
END clkgen ;
ARCHITECTURE RTL of clkgen is
signal gate_cycles_clkgen : std_logic_vector(32 downto 0);
signal delay_cycles_clkgen : std_logic_vector(32 downto 0);
signal total_cycles_clkgen : std_logic_vector(32 downto 0);
signal counter_clkgen : std_logic_vector(32 downto 0);
signal control_clkgen : std_logic;
begin
gate_cycles_clkgen <= '0' & gate_clkgen;
delay_cycles_clkgen <= '0' & delay_clkgen;
total_cycles_clkgen <= gate_cycles_clkgen + delay_cycles_clkgen;
start_proc: process(lclk, start_clkgen)
begin
if (start_clkgen'event and start_clkgen = '1') then
if control_clkgen = '0' then
control_clkgen <= '1';
end if;
end if;
if (lclk'event and lclk = '1') then
if control_clkgen = '1' then
counter_clkgen <= counter_clkgen + 1;
if (counter_clkgen > delay_cycles_clkgen - 1 AND counter_clkgen < total_cycles_clkgen + 1) then
output_clkgen <= '1';
elsif (counter_clkgen = total_cycles_clkgen) then
counter_clkgen <= (others => '0');
output_clkgen <= '0';
control_clkgen <= '0';
end if;
end if;
end if;
end process start_proc;
END RTL;
非常感谢您的帮助.
推荐答案
问题在于您描述元素 control_clkgen 的方式 - 它对两个不同的信号 (lclk 和 start_clkgen).工具告诉你的是嘿，当我试图让你的有效 VHDL 设计适合一个真正的硬件时，我发现没有任何硬件可以实现你想要的. 基本上，没有可以对两个信号(只有一个，通常是时钟)边缘敏感的触发器.
The problem is that in the way you has described the element control_clkgen - it is edge sensitive to two different signals (lclk, and start_clkgen). What the tools are telling you is that "hey, as I am trying to make your valid VHDL design fit into a real piece of hardware, I have found that there are not any pieces of hardware that can implement what you want. Basically, there are no flip flops that can be edge sensitive to two signals (only one, typically the clock.
可能的解决方案:你真的需要control_clkgen对start_clkgen的边缘敏感吗?这是否足够好，或者您能找到另一种解决方案，其中 start_proc 仅对 lclk 敏感，而您只需检查 start_clkgen 是否高?
Possible solution: Do you really need control_clkgen to be sensitive to the edge of start_clkgen? Would it be good enough, or could you find another solution where start_proc is sensitive only to lclk and you simply check if start_clkgen is high?
start_proc: process(lclk)
begin
if (rising_edge(lclk)) then
start_clkgen_d <= start_clkgen;
if (start_clkgen='1' and start_clkgen_d='0') then
if control_clkgen = '0' then
control_clkgen <= '1';
end if;
end if;
end if;
...
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