使用管道屏障代替信号量 [英] Using pipeline barriers instead of semaphores

问题描述

我想确保我正确理解了管道障碍.因此，如果第二个障碍的源阶段晚于第一个障碍的目标阶段，则障碍能够同步两个命令缓冲区.这样对吗?当然，如果命令缓冲区在管道的不同迭代期间执行，我将需要使用信号量.

I want to be sure that I understand pipeline barriers correctly. So barriers are able to synchronize two command buffers provided the source stage of the second barrier is later than the destination stage of the first barrier. Is this correct? Of course I will need to use semaphores if the command buffers execute during different iterations of the pipeline.

在我看来，同步是 Vulkan 中最难掌握的部分.IMO 规范对此还不够清楚.

It seems to me that synchronisation is the hardest part to grasp in Vulkan. IMO the specification isn't clear enough about it.

推荐答案

序言:

适用于 Vulkan Pipeline Barriers 的大部分内容都适用于通用障碍和内存障碍，因此您可以从那里开始构建您的直觉.

Preamble:

Most of what applies to Vulkan Pipeline Barriers applies to generic barriers and memory barriers, so you can start there to build your intuition.

我会注意到，虽然规范不是教程，但它相当清晰易读.同步可能是最难的部分，规范中的描述反映了这一点.最重要的是，尤其是内存屏障对大多数人来说是新奇的(它们通常被高级语言编译器屏蔽了这种概念).

I would note, though the specification is not a tutorial, it is reasonably clear and readable. Synchronization is perhaps the hardest part and the description in specification mirrors that. On top of that, especially memory barriers are novel to most (they are usualy shielded from such concept by higher language compiler).

Pipeline 是工作单元处理方式的抽象方案.有四种类型(虽然 Vulkan 并没有告诉供应商如何做事，只要他们遵守规则即可):

Pipeline is abstract scheme of how a unit of work is processed. There are sort of four types (though Vulkan does not say vendors how to do things as long as they follow the rules):

1. 主机访问伪管道(一级)
2. 转移(一级)
3. 计算(一个阶段)
4. 图形(有很多阶段，即DI→VI→VS→TCS→TES→GS→EFT→FS→LFT→输出)

有特殊的阶段 TOP(在任何事情完成之前)、BOTTOM(在一切完成之后)和 ALL(与所有阶段设置的位域相同).

There are special stages TOP (before anything is done), BOTTOM (after everything is finished), and ALL (which is the same as bitfield with all stages set).

(Action) command 是需要(一个或多个)通过管道的命令.必须记录到命令缓冲区(主机通过vkMapMemory()读写除外).

(Action) command is a command that needs (one or more) passes through the pipeline. It must be recorded to command buffer (with the exception of the host reads and writes through vkMapMemory()).

命令缓冲区是一些命令序列(按记录顺序！).而队列也是一系列记录的命令(从提交的命令缓冲区连接起来).

Command buffer is some sequence of commands (in recorded order!). And queue is too a sequence of recorded commands (concatenated from submited command buffers).

队列在执行命令的顺序上有一定的余地(只要保留用户设置的状态，它就可以重新排列命令)，也可能重叠命令(例如在完成前一个命令的 FS 之前执行下一个命令的 VS).用户定义的同步原语为这个余地设置了一个边界.(也有一些隐含的保证——但最好不要依赖它们并过度同步直到有信心)

The queue has some leeway in which order it executes the commands (it may reorder commands as long as the user-set state is preserved) and also may overlap commands (e.g. execute VS of next command before finishing FS of previous command). User defined synchronization primitives set a boundaries to this leeway. (There are also some implicit guarantees -- but better to not rely on them and oversynchronize until confident)

(也许不幸的是)管道屏障合并了三个独立的方面——执行屏障、内存屏障和布局转换(如果是图像).

(Maybe unfortunately) the Pipeline Barriers amalgamates three separate aspects -- execution barrier, memory barrier and layout transition (if it's image).

执行屏障部分确保在屏障到达执行之前记录的所有命令至少在srcStageMask before 在 Barrier 开始执行 dstStageMask 中指定的阶段(或多个阶段)之后记录的任何命令.

The execution barrier part assures that all commands recorded before the Barrier reached in exececution at least the specified pipeline stage (or stages) in srcStageMask before any of the commands recorded after the Barrier starts executing their specified stage (or stages) in dstStageMask.

它只处理执行依赖而不处理内存！内存屏障 部分确保内存(缓存)被正确刷新并在执行屏障 依赖之间的某处失效(即在依赖命令和阶段之后和之前).

It does handle only execution dependency and not memory! The memory barrier part assures that memory (caches) are properly flushed and invalidated somewhere in between that execution barrier dependency (i.e. after the depending and before the dependant commands and stages).

你提供了什么样的内存依赖以及什么样的来源/消费者(这样驱动程序可以选择适当的动作而不必记住状态本身).典型的写-读依赖(读-读和读-写不需要任何内存同步，写-写通常没有多大意义——为什么你会在没有先读取的情况下覆盖一些数据).

You provide what kind of memory dependency it is and between what kind of sources/consumers (so the driver can choose appropriate action without remembering the state itself). Typicaly write-read dependency (read-read and read-write do not need any memory synchronization and write-write does not usually make much sense -- why would you overwrite some data without reading them first).

在某些硬件上，内存中的不同数据布局可能是有利的(甚至是必需的).在处理内存依赖的同时，数据被重新排序以符合新的指定布局.

Different data layout in memory may be advantegeous (or even necessery) on some HW. In the same time the memory dependency is handeled, the data is reordered to adhere to the new specified layout.

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