PTLsim等CAS模拟器如何实现x86硬件的周期精确模拟? [英] How can CAS simulators like PTLsim achieve cycle accurate simulation of x86 hardware?

问题描述

有人能告诉我像 http://www.ptlsim.org/ 这样的 CAS 软件是如何工作的吗?如果既不知道每条指令使用多少周期的信息，也不知道 CPU 分支预测逻辑，它们如何实现周期精度?或者一切都可以通过 NDA 获得?

Can somebody enlighten me how does CAS software like http://www.ptlsim.org/ work? How do they achieve cycle accuracy if there is neither information how many cycles are used per instruction nor CPU branch prediction logic is known? Or is everything available over NDAs?

我想它们在缓存被命中或遗漏时可能非常准确(也许我错了，但我认为预测内部算法更容易)，但不知道流水线和超标量是如何实现的，我很困惑如何使仿真周期准确.

I suppose they probably can be pretty accurate with caches being hit or missed (maybe I'm wrong but I think it's easier to predict the internal algorithm), but without knowledge how pipelining and superscalarity are implemented I'm confused how to make simulation cycle accurate.

因此，理论上是否可以在基于 x86 的硬件上实现 hard rtos?或者应该签署某种保密协议才能估计每条指令所需的时间?

Consequently, is it theoretically possible to implement hard rtos on x86 based hardware? Or one should sign some sort of NDA to be able to estimate required time per instruction?

推荐答案

第一个问题:如果既不知道每条指令使用多少周期的信息，也不知道 CPU 分支预测逻辑，他们如何实现周期精度?

模拟器确实为足够准确的 CPU 模型提供了周期准确的模拟，但没有为英特尔或 AMD 的当前产品提供开箱即用的模型.英特尔或 AMD 中有权访问所需信息的人员可以创建 RTL 级模型并获得当前处理器的周期精确模拟.英特尔和 AMD 之外的人不能.您仍然可以将公开的已知信息提供给模拟器并获得合理的结果.这些结果将与真实硬件不同.

The simulator does provide a cycle accurate simulation for a sufficiently accurate CPU model but does not come with out-of-the box models for Intel's or AMD's current offerings. Someone at Intel or AMD with access to the required information could create a RTL level model and get cycle accurate simulations for current processors. People outside Intel and AMD cannot. You can still feed publically known information to the simulator and get reasonable results. These results will not be identical to the real hardware.

如果您是软件开发人员并且想要对真实硬件进行基准测试，请使用真实硬件！PLTsim 等模拟器专为(学术)硬件开发人员设计，他们希望测试新的硬件功能，而无需在新芯片上花费数十万美元.

If you are a software developer and want to benchmark real hardware, use real hardware! Simulators like PLTsim are designed for (academic) hardware developers who want to test new hardware features without spending hundreds of thousands of dollars on a new chip.

第二个问题:理论上是否可以在基于 x86 的硬件上实现硬 rtos?

当然，理论上是可能的.您需要考虑所有情况下所有输入的每个代码段的绝对最坏情况.实际问题是像Core 2这样的处理器非常复杂，处理器的状态非常大.此外，这些处理器并非设计为在时序方面具有确定性的行为.一个真正困难的 RTOS 必须非常保守.最后，正如您所观察到的，英特尔和 AMD 以外的人无法获得做出这些保守假设所需的所有信息.在实践中，传递最新和最好的 CPU 而不是使用具有确定性时序的较旧、更简单的 CPU 是合理的.

Of course it is theoretically possible. You would need to consider the absolute worst case for each code segment for all inputs under all circumstances. The practical problem is that processors like Core 2 are very complex and the state of the processor is enormous. Additionally these processors are not designed to behave deterministically with respect to timing. A really hard RTOS would have to be extremely conservative. Finally, as you correctly observe, people outside Intel and AMD don't have access to all the information required to make those conservative assumptions. In practice it is resonable to pass on the latest and greatest cpus and instead use older, simpler cpus that have a deterministic timing.

另一方面，如果 RTOS 不必非常实时，您总是可以包括一些安全裕度并希望最好.;-)

On the other hand, if the RTOS does not have to be really hard real time, you can always just include some safety margin and hope for the best. ;-)

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