现代处理器有多少个 EAX 寄存器? [英] How many EAX register do modern processor have?

问题描述

我是汇编编程的初学者，想知道单个 EAX 通用寄存器可以容纳多少和多少.作为初学者，似乎每个 eax、ebx 等都只有一个.寄存器.

I am a beginner in assembly programming and was wondering how many and how much can a single EAX general purpose register can hold. As a beginner it seems there is only one each eax,ebx,etc. registers.

推荐答案

这些是逻辑寄存器名称.您假设每个正在运行的线程在程序中的任何给定点都有一个有效的 RAX 值是正确的(顺便说一句 - 对于超线程，这意味着每个内核有两个)，但实际上现代硬件不包含单个值而是多个值.

These are logical register names. You are right in assuming each running thread has a single RAX value valid at any given point in the program (by the way - with hyperthreading this means two per core), but in fact modern HW doesn't hold a single value but multiple ones.

现代无序 CPU 将尝试根据源代码准备情况执行指令，因此对于下一个程序，例如:

A modern out of order CPU will attempt to perform instructions based on source readiness, so for the next program for e.g.:

mov rax, 1  ; #1
add rax, 2  ; #2
mov rax, 3  ; #3
add rax, 4  ; #4

CPU 可以在解码后立即执行指令 #1 和 #3，因为它们不需要满足任何依赖关系(并且运行 rax 中的旧值).此外，指令#2 可以在之后并行执行，因为每个指令仅取决于前一条指令.但是，为了在硬件中允许这样做，您需要能够将结果保存在某个临时寄存器中 - 因为他们想出了 register renaming - 而不是调用每个操作的结果 rax，每条指令都会分配一个新的具有唯一ID的物理寄存器，并更新rax现在的一些全局表(通常称为RAT - 寄存器别名表)由物理寄存器#37 或其他表示.

The CPU can perform instructions #1 and #3 as soon as they're decoded, since they require no dependencies to be fulfilled (and run over the old value in rax). Additionally, instruction #2 can be performed in parallel right afterwards, as each depends only on the preceding instruction. However, to allow that in HW, you need to be able to keep the results in some temporary register - for that they came up with register renaming - instead of calling the result of each operation rax, each instruction will assign a new physical register with some unique ID, and update some global table (often called RAT - register alias table) that rax is now represented by physical register #37 or whatever.

重要的部分是必须使用正确的版本来维护源代码，因此它们也同时被重命名.指令#2 不会使用rax，而是使用指令#1 的目的地.Inst #4 将类似地使用 inst #3 的结果.如果您接受重命名是按顺序，并且别名已正确更新，则很容易看出从逻辑寄存器名称到物理寄存器名称的每次转换都维护了正​​确的程序顺序.

The important part is that the sources must be maintained using the correct versions, so they're also renamed at the same moment. Instruction #2 won't use rax, but instead use the destination of inst #1. Inst #4 will similarly use the result of inst #3. If you accept that the renaming is done in-order, and the aliases are updated correctly, it's easy to see that each translation from logical to physical register name maintains the correct program order.

因此，虽然对于管道中的每条指令，您都有一个正确的"rax 寄存器，这不一定是相同的物理寄存器.从某种意义上说，您可以说您有多个不同的逻辑寄存器副本，每个副本仅在下一次写入相同的逻辑名称之前有效.

Therefor, while you have a single "correct" rax register with regards to each instruction alive in the pipeline, this isn't necessarily the same physical register. In a sense, you can say that you have multiple different copies of the logical register, each one valid only until the next write to the same logical name.

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