了解分支预测 [英] Understanding branch prediction
问题描述
有一些关于分支预测的问题,我无法确定.假设我必须使用静态分支预测器.
<块引用>- 应该在流水线的哪个阶段进行分支预测?
- 如何知道预测出错了?数据路径如何知道发生了错误预测?
- 如果知道发生了错误预测,它如何发送信号以占用未采用的分支?
- 出现问题后,我必须使用之前没有使用的地址.同时,如果发生了一些内存写入或寄存器写入怎么办?如何防止它发生?
即使建议了一些带有数据路径的适当引用,这也会非常有帮助.提前致谢.
- At which stage of the pipeline should branch prediction happen?
- How to know that a prediction has gone wrong? How does the datapath come to know that a misprediction has happened?
- If it comes to know that a misprediction has happened, how does it send the signal to take up the not-taken branch?
- After it has gone wrong, I have to take up that address that was not taken earlier. In the meanwhile, what if some memory-write or register-write has happened? How to prevent it from happening?
It will be very helpful even if some proper references with datapath in them are suggested. Thanks in advance.
I took my time reading the reference manual for the Cortex-A8: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf
From section 5.1:
The processor contains program flow prediction hardware, also known as branch prediction. With program flow prediction disabled, all taken branches incur a 13-cycle penalty. With program flow prediction enabled, all mispredicted branches incur a 13-cycle penalty.
Basically this means that static branch prediction always assume branches to be false. This is different compared to PowerPC that have "special instructions" for hinting the processor about taken/not-taken branches (postfix +/-).
From section 1.3.1:
The instruction fetch unit predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.
- Instruction Fetch, the first stage, makes the prediction.
From section 7.6.2:
An instruction can remain in the pipeline between being fetched and being executed. Because there can be several unresolved branches in the pipeline, instruction fetches are speculative, meaning there is no guarantee that they are executed. A branch or exceptional instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions. Fetches or instruction table walks that begin without an empty pipeline are marked speculative. If the pipeline contains any instruction up to the point of branch and exception resolution, then the pipeline is considered not empty.
I interpret this as nothing reaches the execution stage while a branch is being processed. If mispredition occurs, as discovered when executing a branch in Instruction Execute, all instructions in the pipeline are "flushed". They are never executed. That should answer question 2 and 4. Not so sure about how the "marking" is performed.
- I don´t know how it sends the signal. As far as I can tell the reference manual does not cover that part. Guess it´s magic.
(For the record I find the PowerPC reference manuals (e500/e600) I´m used to being much easier to understand because of the many instruction timing samples.)
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