数据缓存和指令缓存是什么意思? [英] What is meant by data cache and instruction cache?

问题描述

从这里:

指令和数据有不同的访问模式，访问不同的内存区域.因此，两者都拥有相同的缓存说明和数据可能并不总是有效.

Instructions and data have different access patterns, and access different regions of memory. Thus, having the same cache for both instructions and data may not always work out.

因此，有两个缓存是很常见的:一个指令缓存只存储指令，一个只存储数据的数据缓存.

Thus, it's rather common to have two caches: an instruction cache that only stores instructions, and a data cache that only stores data.

知道指令和数据之间的区别很直观，但现在我不确定在这种情况下的区别?什么构成数据并放入数据缓存，什么构成指令并放入指令缓存?

It's intuitive to know the distinction between instructions and data, but now I'm not show sure of the difference in this context? What constitutes as data and gets put into a data cache and what constitutes as instructions and gets put into an instruction cache?

我知道 ARM 汇编.任何需要 STR、LDR、LDMF 或 STMFD 的东西会使用数据缓存吗?但从技术上讲，STR、LDR、LDMF 和 STMFD 都是指令，所以我这就是为什么我很困惑.数据"必须始终与指令"一起存在吗?.data 部分中的数据是否被视为任何内容?

I know ARM assembly. Would anything requiring STR, LDR, LDMF or STMFD use the data cache? But technically speaking STR, LDR, LDMF and STMFD are all instructions so I this is why I'm confused. Must "data" always exist with an "instruction"? Is data considered anything in the .data section?

例如 LDR R1, =myVar 那么 LDR 会进入指令缓存，而 myVar 的内容会进入数据缓存吗?或者它不是那样工作的?

For example LDR R1, =myVar then would LDR go into the instruction cache and the contents of myVar go into the data cache? Or does it not work like that?

指令和数据有不同的访问模式有人能详细说明一下吗?

Instructions and data have different access patterns Could someone please elaborate?

我在一篇有用的帖子上发表的评论凸显了我的理解困难:

This comment I made on a helpful post highlights my difficulty understanding:

"这个想法是，如果一条指令已经从内存中加载，它是可能很快会再次使用"，但这是了解下一个的唯一方法指令是阅读它.这意味着内存读取(你不能说它已经在缓存中，因为一条新指令是红色的).所以我还是没明白重点?假设刚刚发生了 LDR 指令，那么现在LDR 位于数据缓存中.也许会发生另一个 LDR 指令，也许不会，我们不能确定所以我们必须真正阅读下一个指令 - 从而违背了缓存的目的.

"The idea is that if an instruction has been loaded from memory, it's likely to be used again soon" but the only way to know the next instruction is to read it. That means a memory read (you can't say it's already in cache because a new instruction is being red). So I still don't see the point? Say a LDR instruction just happened, so now LDR is in the data cache. Maybe another LDR instruction will happen, maybe it won't, we can't be sure so we have to actually read the next instruction - thus defeating the purpose of cache.

推荐答案

指令提取可以分块完成，假设大部分时间您将连续运行许多指令.因此指令提取可以更有效，每个事务可能有少数或更多时钟的开销，然后是内存准备数据的延迟，然后是事务大小的每个总线宽度的时钟.例如，8 个字或指令可以说是 5+n+8 个时钟，这比一次一条指令 (5+1+1)*8 更有效率.

Instruction fetches can be done in chunks with the assumption that much of the time you are going to run through many instructions in a row. so instruction fetches can be more efficient, there is likely a handful or more clocks of overhead per transaction then the delay for the memory to have the data ready then a clock per width of the bus for the size of the transaction. 8 words or instructions might be say 5+n+8 clocks for example, that is more efficient than one instruction at a time (5+1+1)*8.

另一方面，假设数据将在大部分时间按顺序读取，因此额外的周期可能会受到伤害，只获取请求的数据(直到内存或总线的宽度)是免费赠品).

Data on the other hand it is not that good of an assumption that data will be read sequentially much of the time so additional cycles can hurt, only fetch the data asked for (u p to the width of the memory or bus as that is a freebie).

在我所知道的 ARM 上，L1 缓存 I 和 D 是分开的，而 L2 是组合在一起的.L1 不在 axi/amba 总线上，并且可能比 L2 的访问效率更高，并且在 L2 之后是 amba/axi(几个周期的开销加上时间加上每个事务的每个总线宽度的数据一个时钟).

On the ARMs I know about the L1 cache I and D are separate, L2 they are combined. L1 is not on the axi/amba bus and is likely more efficient of an access than the L2 and beyond which are amba/axi (a few cycles of overhead plus time plus one clock per bus width of data for every transaction).

对于标记为可缓存的地址空间(如果 mmu 已打开)，L1 和 L2 将获取缓存行而不是单个数据项，并且可能超过获取指令的 I 数据量取.

For address spaces that are marked as cacheable (if the mmu is on) the L1 and as a result L2 will fetch a cache line instead of the individual item for data and perhaps more than a fetch amount of I data for an instruction fetch.

您的每条 ldr 和 ldm 指令都将导致数据周期，如果地址可缓存，则可以进入 L2 和 L1 缓存(如果尚未存在).指令本身如果在可缓存的地址，也将进入 L2 和 L1 缓存(如果尚未存在).(是的，有很多旋钮可以控制哪些是可缓存的，哪些是不可缓存的，不想涉及这些细微差别，只是为了讨论而假设所有这些指令获取和数据访问都是可缓存的.

Each of your ldr and ldm instruction are going to result in data cycles that can if the address is cacheable go into the L2 and L1 caches if not already there. the instruction itself also if at a cacheable address will go into the L2 and L1 caches if not already there. (yes there are lots of knobs to control what is cacheable and not, dont want to get into those nuances, just assume for sake of the discussion all of these instruction fetches and data accesses are cacheable).

如果您有循环或再次运行该代码，您可能希望将刚刚执行的指令保存在缓存中.此外，高速缓存行中的指令将受益于更高效访问所节省的开销.但是如果你只通过一小部分缓存线执行，那么总的来说这些周期是一种浪费，如果这种情况发生太多，那么缓存会使事情变慢.

You would want to save instructions just executed in the cache in case you have a loop or run that code again. Also the instructions that follow in the cache line will benefit from the saved overhead of the more efficient access. but if you only execute through a small percentage of the cache line then overall those cycles are a waste, and if that happens too much then the cache made things slower.

一旦某些内容在缓存中，那么下次读取(或根据设置写入)时，将使用缓存副本，而不是慢速内存中的副本.最终(取决于设置)如果某个项目的缓存副本由于写入(str，stm)而被修改，并且需要将一些新访问保存在缓存中，那么旧的将被驱逐回慢速内存并从缓存减慢内存发生.你的指令没有这个问题，指令基本上是只读的，所以你不必把它们写回慢速内存，理论上缓存副本和慢速内存副本是一样的.

Once something is in a cache then the next time it is read (or written depending on the settings) the cache copy is the one that is used, not the copy in slow memory. Eventually (depending on settings) if the cache copy of some item has been modified due to a write (str, stm) and some new access needs to be saved in the cache then an old one is evicted back to slow memory and a write from the cache to slow memory happens. You dont have this problem with instructions, instructions are basically read-only so you dont have to write them back to slow memory, in theory the cache copy and the slow memory copy are the same.

ldr r1,=myvar

会导致电脑相对负载

ldr r1,something
...
something: .word myvar

ldr 指令将成为缓存行提取、指令提取(以及更多指令)的一部分.这些将保存在手臂上 L1 缓存的 I 部分和 L2 的共享部分(如果启用等).当该指令最终执行时，某物的地址将经历数据读取，如果在该区域中为该读取启用了缓存，那么它也将进入 L2 和 L1 缓存(D 部分)(如果尚未存在).如果您立即循环并再次运行该指令，那么理想情况下该指令将位于 L1 缓存中，并且获取它的访问时间非常快，总共只有几个时钟.数据也将在 L1 高速缓存中，并且也将是一些要读取的时钟.

the ldr instruction will be part of a cache line fetch, an instruction fetch (along with a bunch more instructions). these will be saved in I part of the L1 cache on an arm and the shared part of L2 (if enabled, etc). When that instruction is finally executed then the address for something will experience a data read, which if caching is enabled in that area for that read then it will also go into the L2 and L1 cache (D part) if not already there. If you loop around and run that instruction again right away then ideally the instruction will be in the L1 cache and the access time to fetch it is very fast a handful of clocks total. The data also will be in the L1 cache and will also be a handful of clocks to read.

我上面提到的 5+n+8，一些时钟开销(5 只是一种可能性，它可能因设计和其他并行情况而异).N 取决于较慢的内存速度.n 对于 dram 来说相当大，所以缓存 l2 和 L1 快得多，这就是为什么缓存在那里是为了减少每次 dram 访问的大量时钟周期，无论是否有效.

The 5+n+8 I mentioned above, some number of clocks of overhead (5 is just a possibility, it can vary both by the design and by what else is going on in parallel). the N depends on the slower memory speeds. that n is quite large for dram, so the caches l2 and L1 are much much faster, and that is why the cache is there at all to reduce the large number of clock cycles for every dram access, efficient or not.

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