ARM IT 条件指令汇编器 (armcc) [英] ARM IT conditional instruction assembler (armcc)

问题描述

为什么下面编译:

 
    ITE EQ         
    MRSEQ  R0, MSP
    MRSNE   R0, PSP        

但这不是:

 
    ITT NE

    MRSNE   R0, PSP

    MRSEQ  R0, MSP 

是否有可能同时执行 MRSNE R0、PSP 和 MRSEQ R0、MSP(这是我的情况)?

Is it possible, that both MRSNE R0, PSP and MRSEQ R0, MSP execute (this is my case)?

This compiles:

 
    ITT NE         
    MRSNE   R0, PSP       
    MRSNE  R0, MSP 

它是 ARM 标准吗?

Is it ARM standard?

推荐答案

但这不是:

ITT NE
MRSNE   R0, PSP
MRSEQ  R0, MSP

首先，您有一些概念问题.ITT 是什么?先来一段历史.早期的 ARM CPU 不支持 Thumb(16 位)，也不支持 Thumb2(混合 16/32 位)编码.对于纯 ARM，很大一部分(4 个前导位)专用于条件执行.Thumb 指令集不支持条件执行.对于 Thumb2(您想要的 Cortex-M 部分)，条件执行有所不同.不是在每条指令中编译条件，而是在条件寄存器中设置 8 位的 it 指令.

First you have some concept issues. What is ITT all about? First some history. The early ARM CPUs did not support Thumb (16bit), nor Thumb2 (mix 16/32bit) encoding. For the pure ARM, a large part (4 leading bits) are dedicated to conditional execution. The Thumb instruction set does not support conditional execution. For the Thumb2 (what you want on your Cortex-M part), there is a variation on conditional execution. Instead of compiling a condition in each instruction, there is an it instruction which sets 8 bits in the condition register.

it 指令与测试进行比较(EQ、NE、LO 等).然后它给出最多四个条件指令.来自 Cortex-A 程序员手册，

The it instruction gives a comparison to test (EQ, NE, LO, etc). It then gives up to four conditionals instructions. From the Cortex-A programmer's manual,

第 A.1.34 节

IT(If-then)组成了四个以下条件指令(称为IT块).条件可以全部相同，也可以是其他条件的逻辑逆.IT是ARM状态下的伪指令.

IT (If-then) makes up to four following instructions conditional (known as the IT block). The conditions can all be the same, or some can be the logical inverse of others. IT is a pseudo-instruction in ARM state.

语法:IT{x{y{z}}} {cond}
其中: cond 是条件代码.请参阅第 6.1.2 节，其中指定了 IT 块中第一条指令的条件.
x 、 y 和 z 指定 IT 块中第二、第三和第四条指令的条件开关，例如，ITTET.条件开关可以是:

Syntax: IT{x{y{z}}} {cond}
where: cond is a condition code. See Section 6.1.2 which specifies the condition for the first instruction in the IT block.
x , y and z specify the condition switch for the second, third and fourth instructions in the IT block, for example, ITTET. The condition switch can be either:

• T (Then)，将条件 cond 应用于指令.
• E (Else)，将 cond 的逆条件应用于指令.

为了同时支持 Thumb2 和 ARM 汇编器，一种名为 统一汇编语言已创建.^{参考:统一语法}

In order to support both Thumb2 and ARM assembler, a new mode called unified assembler language was created.^{Ref: Unified Syntax}

对于纯 ARM，IT 的计算结果为零.指令用条件编码.对于 Thumb2，它准备条件寄存器以设置条件位.ARM汇编器共有三种模式；.arm、.thumb 和 .unified.还有 .code 32 和 .code 16.根据使用的模式和特定的汇编程序(Gnu、ARM 等)，您将收到不同的警告和/或错误.但是，对于您的序列，此模式永远不会失败，

For pure ARM, the IT evaluates to nothing. The instructions are encoded with the conditions. For the Thumb2, it primes the condition registers to setup the condition bits. There are three modes of ARM assembler; .arm, .thumb and .unified. Also .code 32 and .code 16. Depending on the mode in use and the particular assembler (Gnu, ARM, etc) you will get different warnings and/or errors. However, this pattern will never fail for your sequence,

   ITE    NE       ; first NE, 2nd !NE = EQ (Thumb2)
   MRSNE  R0, PSP  ; first NE               (ARM)
   MRSEQ  R0, MSP  ; 2nd !NE = EQ           (ARM)

MRS 指令是IT 块".在您的情况下，您使用 thumb2 特殊寄存器，因此 统一语法 对于手头的任务没有多大意义.请参阅下面的注释.

The MRS instructions are the 'IT block'. In your case, you use thumb2 special registers, so the unified syntax doesn't make a lot of sense for the task at hand. See note below.

为了制作统一的IT 块，您应该注意一些规则.

There are some rules you should be aware of to make unified IT blocks.

1. IT 块不应设置条件代码.即，cmpne 指令.
2. 您不应进入IT 块.
3. 我们总是以IT开头，所以IT中的cond必须匹配第一条指令.
4. 以下指令必须匹配 cond，如果是 'T'，或者 !cond 如果是 'E'.
5. 您不应更改条件寄存器PSR、cpsr 等.^{请参阅注意}
6. 您只能混合相反的类型.例如，

1. The IT block should not set the condition codes. Ie, cmpne instruction.
2. You should not branch into the IT block.
3. We always start with IT, so the cond in the IT must match the first instruction.
4. Following instruction must match cond, if 'T' or !cond if 'E'.
5. You should not alter the condition register PSR, cpsr, etc. ^{See Note}
6. You can only mix opposite types. For instance,

     movlo  r1, #-1
     moveq  r1, #0
     movhi  r1, #1

适用于 ARM，但不适用于 Thumb2.就您而言，您违反了规则4"并出现错误.

Would work in ARM, but not Thumb2. In your case, you broke rule '4' and get an error.

示例:

.text
.syntax unified
ITE NE          @ first NE, 2nd !NE = EQ (Thumb2) 
movne R0, #1    @ first NE (ARM) 
moveq R0, #2    @ 2nd !NE = EQ (ARM)

反汇编的ARM，

00000000 <.text>:
   0:   13a00001        movne   r0, #1
   4:   03a00002        moveq   r0, #2

拆解thumb2,

00000000 <.text>:
   0:   bf14            ite     ne
   2:   2001            movne   r0, #1
   4:   2002            moveq   r0, #2

对于 thumb2，这是没有 ITE 指令的等价物，

For the thumb2, this is the equivalent without the ITE instruction,

00000000 <.text>:
   0:   2001            movs    r0, #1
   2:   2002            movs    r0, #2

即，两步设置条件码.反汇编程序中的第二个数字当然是机器代码.对于thumb2 OS/scheduler，它会恢复条件寄存器，恢复IT状态，你可以进入到中间>IT 块.也可以手动执行此操作(但是，它可能高度特定于 CPU，并且我所知道的没有记录在案).

Ie, two moves setting the condition codes. The 2nd number in the dis-assembler is the machine code of course. For a thumb2 OS/scheduler, it will restore the condition register which restores the IT state and you can enter into the middle of the IT block. It is also possible to do this manually (however, it maybe highly CPU specific and is not documented that I know of).

注意:对于改变PSR的Cortex-M调度程序代码，您需要使用分支.这些寄存器控制 IT 块的执行.您不应修改 IT 块中的 PSR.这同样适用于任何上下文恢复指令；我不是 100% 熟悉涉及更改活动 PSR 的 Cortex-M 模式切换.

Note: For Cortex-M scheduler code which alters the PSR, you need to use branches. These registers are controlling the IT block execution. You should not modify the PSR in the IT block. The same applies for any context restore instructions; I am not 100% familiar with Cortex-M mode switching which involves changing the active PSR.

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