ARM 的启动过程是怎样的? [英] What is the booting process for ARM?

问题描述

众所周知，对于X86架构:按下电源键后，机器在0xFFFFFFF0处开始执行代码，然后开始执行BIOS中的代码以进行硬件初始化.BIOS 执行后，它使用引导加载程序将操作系统映像加载到内存中.最后，操作系统代码开始运行.对于ARM架构，使用按下电源键后的启动过程是怎样的?谢谢！

As we know, for X86 architecture: After we press the power button, machine starts to execute code at 0xFFFFFFF0, then it starts to execute code in BIOS in order to do hardware initialization. After BIOS execution, it use bootloader to load the OS image into memory. At the end, OS code starts to run. For ARM architecture, what is the booting process after use press the power button? Thanks!

推荐答案

目前ARM架构中有两种异常模型(reset也是一种异常):

Currently, there are two exception models in the ARM architecture (reset is considered a kind of exception):

经典模型，用于Pre-Cortex芯片和当前Cortex-A/R芯片.其中，0 处的内存包含几个异常处理程序:

The classic model, used in pre-Cortex chip and current Cortex-A/R chips. In it, the memory at 0 contains several exception handlers:

 Offset  Handler
 ===============
 00      Reset 
 04      Undefined Instruction
 08      Supervisor Call (SVC)
 0C      Prefetch Abort
 10      Data Abort
 14      (Reserved)
 18      Interrupt (IRQ)
 1C      Fast Interrupt (FIQ)

当异常发生时，处理器只是从一个特定的偏移量开始执行，所以通常这个表包含单指令分支到代码中更进一步的完整处理程序.典型的经典向量表如下所示:

When the exception happens, the processor just starts execution from a specific offset, so usually this table contains single-instruction branches to the complete handlers further in the code. A typical classic vector table looks like following:

00000000   LDR   PC, =Reset
00000004   LDR   PC, =Undef
00000008   LDR   PC, =SVC
0000000C   LDR   PC, =PrefAbort
00000010   LDR   PC, =DataAbort
00000014   NOP
00000018   LDR   PC, =IRQ
0000001C   LDR   PC, =FIQ

在运行时，向量表可以重定位到 0xFFFF0000，这通常被实现为一个紧密耦合的内存范围，以实现最快的异常处理.但是，上电复位通常从0x00000000开始(但在某些芯片中可以通过处理器引脚设置为0xFFFF0000).

At runtime, the vector table can be relocated to 0xFFFF0000, which is often implemented as a tightly-coupled memory range for the fastest exception handling. However, the power-on reset usually begins at 0x00000000 (but in some chips can be set to 0xFFFF0000 by a processor pin).

新的微控制器模型用于 Cortex-M 系列芯片.在那里，0 处的向量表实际上是一个向量表(指针)，而不是指令.第一个条目包含 SP 寄存器的启动值，第二个条目是复位向量.这允许直接在 C 中编写复位处理程序，因为处理器设置了堆栈.同样，该表可以在运行时重新定位.Cortex-M 的典型向量表如下所示:

The new microcontroller model is used in the Cortex-M line of chips. There, the vector table at 0 is actually a table of vectors (pointers), not instructions. The first entry contains the start-up value for the SP register, the second is the reset vector. This allows writing the reset handler directly in C, since the processor sets up the stack. Again, the table can be relocated at runtime. The typical vector table for Cortex-M begins like this:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                [...more vectors...]

请注意，在 OMAP3 或 Apple 的 A4 等现代复杂芯片中，执行的第一段代码通常不是用户代码，而是片上 Boot ROM.它可能会检查各种条件以确定从何处加载用户代码以及是否完全加载它(例如，它可能需要有效的数字签名).在这种情况下，用户代码可能必须符合不同的启动约定.

Note that in the modern complex chips such as OMAP3 or Apple's A4 the first piece of code which is executed is usually not user code but the on-chip Boot ROM. It might check various conditions to determine where to load the user code from and whether to load it at all (e.g. it could require a valid digital signature). In such cases, the user code might have to conform to different start-up conventions.

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