乱序执行会导致推测性内存访问吗? [英] Can out-of-order execution lead to speculative memory accesses?

问题描述

当一个乱序处理器遇到类似的事情

When a out-of-order processor encounters something like

LOAD R1, 0x1337
LOAD R2, $R1
LOAD R3, 0x42

假设所有访问都会导致缓存未命中，处理器是否可以在请求 $R1 甚至 0x1337 的内容之前向内存控制器请求 0x42 的内容?如果是这样，假设访问 $R1 会导致异常(例如分段错误)，我们可以认为 0x42 是推测加载的，对吗?

Assuming that all accesses will result in a cache miss, can the processor ask the memory controller for the contents of 0x42 before the it asks for the content of $R1 or even 0x1337? If so, assuming that accessing $R1 will result in a exception (e.g., segmentation fault), we can consider that 0x42 was loaded speculatively, correct?

顺便说一句，当加载存储单元向内存控制器发送请求时，它能否在收到前一个请求的答案之前发送第二个请求?

And by the way, when a load-store unit sends a request to the memory controller, can it send a second request before receiving the answer to the previous one?

我的问题没有特别针对任何架构.欢迎提供与任何主流架构相关的答案.

My question doesn't target any architecture in particular. Answers related to any mainstream architecture are welcomed.

推荐答案

您的问题的答案取决于您的 CPU 的内存排序模型，这与允许乱序执行的 CPU 不同.如果 CPU 实现了 Total store ordering(例如 x86 或 Sparc)，那么您的问题的答案是 0x42 将不会在 0x1337 之前加载

Answer to your question depends on the memory ordering model of your CPU, which is not the same as the CPU allowing out of order execution. If the CPU implements Total store ordering (eg x86 or Sparc) then the answer to your question is 0x42 will not be loaded before 0x1337

如果 cpu 实现了一个宽松的内存模型(例如 IA-64、PowerPC、alpha)，那么在没有内存栅栏指令的情况下，所有的赌注都将被首先访问.除非您在做 IO 或处理多线程代码，否则这应该没有多大意义.

If the cpu implements a relaxed memory model (eg IA-64, PowerPC, alpha), then in the absence of a memory fence instruction all bets are off as to which will be accessed first. This should be of little relevance unless you are doing IO, or dealing with multi-threaded code.

您应该注意到某些 CPU(例如 Itanium)确实具有宽松的内存模型(因此读取可能会乱序)但没有任何乱序执行逻辑，因为它们希望编译器对指令和推测指令进行排序一种最佳方式，而不是在 OOE 上花费硅空间

you should note that some CPU's (eg Itanium) do have relaxed memory models (so reads may be out of order) but do NOT have any out of order execution logic since they expect the compiler to order the instructions and speculative instructions in an optimal way rather than spend silicon space on OOE

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