对于ARM，为什么单条STM指令一般比多条STR指令快? [英] For ARM, why a single STM instruction is generally faster than multiple STR instructions?

问题描述

是不是跟一些预取技术有关?还是具有DDR访问时序特性?

Is it related to some prefetch technology? Or with DDR access timing characteristics?

推荐答案

IIRC 从 ARMv5TE 开始，写入缓冲区和 L1 缓存的路径为 64 位宽，以容纳 LDRD/STRD 指令.这允许 STM 每个周期写入两个寄存器.

IIRC starting with ARMv5TE the path to the write buffer and the L1 caches is 64bit wide to accomodate the LDRD/STRD instructions. This allows STM to write two registers per cycle.

您还将节省一点 L1 指令缓存，并且在双核上只使用一个流水线，这也是一个额外的好处.

You'll also save a bit of L1 instruction-cache and use only one pipeline on dual-issue cores, which is also an additional gain.

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