ARM 分支指令地址如何工作? [英] How does an the ARM branch instruction address work?

问题描述

我知道一条 ARM 指令的大小为 32 位，因此在内存中它占用 4 个内存位置(每个位置可以存储 8 位)

I know that an ARM instruction is 32 bits in size and therefore in memory it take up 4 memory locations (each location can store 8 bits)

但是我对分支指令地址的工作方式感到困惑

But am confused on how a branch instruction address works

当使用例如一个分支指令

When using e.g. a Branch instruction

4 位用于操作条件的 4 位24 位用于分支位置

4 bits are used for the operation 4 bits for the condition 24 bits for where to branch

为什么地址是 4 * 24 位?- 我以为每个指令地址都是 32 位

Why is an address 4 * 24 bits? - I thought every instruction address was 32 bits

作为偏移量的 24 位数字是什么意思?

what does it mean by the 24 bit number being an offset?

推荐答案

来自 ARM7TDMI 手册:

From the ARM7TDMI manual:

分支指令包含有符号 2 的补码 24 位偏移量.这是左移两位，符号扩展为 32 位，并添加到 PC.因此该指令可以指定一个 +/- 32Mbytes 的分支.

Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes.

Offset 在这种情况下意味着它相对于当前的 PC.

Offset in this case means that it's relative to the current PC.

偏移量移位 2 位(即乘以 4)的原因是每条指令都需要字对齐，即指令必须位于 4 的倍数的地址上.两个最低有效位所有这样的地址总是零.由于您知道它们始终为零，因此您可以通过省略这两个最低有效位来将 26 位偏移存储为 24 位.

The reason the offset is shifted by 2 bits (i.e. multiplied by 4) is that every instruction is required to be word aligned, i.e. instructions have to be located at an address that is a multiple of 4. The two least significant bits of all such addresses are always zero. Since you know that they are always zero you can store a 26-bit offset in 24 bits by omitting those two least significant bits.

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