LDMIA 指令在 Cortex M4 中的外部 SRAM 上无法正常工作 [英] LDMIA instruction not working correctly on external SRAM in cortex M4
问题描述
我在拇指模式下使用 STM32L486ZG 板.我正在运行一个没有任何 RTOS 的简单裸机应用程序.我使用 FSM 将外部 SRAM 连接到电路板.外部 SRAM 位于地址 0x60000000.系统已初始化并以 72MHz 的频率运行(我已经在 18-80MHz 的频率下尝试过这个问题)，现在在我的主函数中，我有以下代码:
I am using STM32L486ZG board in thumb mode. I am running a simple bare-metal application without any RTOS. I have external SRAM connected to the board using FSM. The external SRAM is located at address 0x60000000. The system is initialized and running at 72MHz (i have tried this issue with frequency from 18-80 MHz) now in my main function i have following code:
int main(){
asm volatile (
"push {r0}\n"
"mov r0, #0x60000000\n"
"add r0, #0x400\n"
"stmdb r0!, {r1-r12}\n"
"ldmia r0!, {r1-r12}\n"
"pop {r0}\n"
);
}
根据这段代码，在这个 main 函数执行之后，没有寄存器应该被改变，但是在下面的指令之后就不是这样了
According to this code no register should be changed after this main function has executed, but that's not the case after the following instruction
ldmia r0!, {r1-r12}
即r9 执行后不正确.stmdb 指令工作正常，但 ldmia 未正确加载数据.我已经通过查看内存中的内容验证了这一点.
i.e. r9 is not correct after execution. stmdb instruction is working correctly but ldmia is not loading the data correctly. I have verified this by viewing the contents from memory.
这个问题对于 ldmia 指令中的任何参数都存在:第 9 个寄存器总是受到影响.
This issue is persistent with any arguments in the ldmia instruction: the 9th register is always affected.
说明:假设我正在调试这段代码，接下来要执行的指令是:
Explanation: Lets say I am debugging this code and the next instruction to execute is this:
stmdb r0!, {r1-r12}
升压后所有这些寄存器都保存在内存中，r0的值为0x600003d0
after stepping up all these registers have been saved in the memory and value of r0 is 0x600003d0
内存内容:
0x600003D0 00000000 40021008 0000000C .......@....
0x600003DC 40000000 00000000 00000000 ...@........
0x600003E8 20017FEC 00000000 00000000 ì.. ........
0x600003F4 00000000 00000000 00000000 ............
寄存器内容:
r0 0x600003d0
r1 0x00000000
r2 0x40021008
r3 0x0000000c
r4 0x40000000
r5 0x00000000
r6 0x00000000
r7 0x20017fec
r8 0x00000000
r9 0x00000000
r10 0x00000000
r11 0x00000000
r12 0x00000000
这说明所有的寄存器都成功保存在内存中了.现在我执行下一条指令
this shows that all the registers are successfully saved in the memory. Now i step the next instruction
ldmia r0!, {r1-r12}
在这之后这些是寄存器的内容:
after this these are the contents of registers:
r0 0x60000400
r1 0x00000000
r2 0x40021008
r3 0x0000000c
r4 0x40000000
r5 0x00000000
r6 0x00000000
r7 0x20017fec
r8 0x00000000
r9 0x555555d5
r10 0x00000000
r11 0x00000000
r12 0x00000000
如您所见，除了 r9 之外，所有寄存器都恢复了，奇怪的是它的值从 0x60000000 而不是 0x600003F0弹出"代码>.
as you can see all the registers are restored except r9 which oddly has its value "pop"ed from 0x60000000 instead of 0x600003F0.
知道是什么导致了这个问题.我正在使用Jlink写入flash.
Any idea what could be causing this issue. I am using Jlink to write into flash.
附言当寄存器保存到片上 SRAM 而不是外部 SRAM 时，不会发生此问题；
P.S. This issue doesn't occur when the registers are saved to onchip SRAM as opposed to external SRAM;
编辑如果指令
ldmia r0!, {r1-r12}
分为两部分，例如:
ldmia r0!, {r1-r6}
ldmia r0!, {r7-r12}
那么所有的寄存器都恢复成功了
then all the registers are restored successfully
推荐答案
您需要阅读 STM32L4xx6xx 芯片限制.FMC 不支持第 2.2.4 节读取 9 个字或更多字的突发访问.( DocID026121 Rev 4 ) 可从 ST 获得.
You need to read the STM32L4xx6xx Silicon Limitations. Section 2.2.4 Read burst access of nine words or more is not supported by FMC. ( DocID026121 Rev 4 ) available from ST.
"CPU 读突发访问等于或大于 9 个寄存器到 FMC 返回损坏的数据从第 9 个读取的单词开始.这些突发只能由 Cortex®-M4 CPU 生成而不是由其他主机(即不是由 DMA).当堆栈重新映射到 FMC 上的外部存储器并且POP 操作使用 9 个或更多寄存器执行.当 LDM/VLDM 操作与 9 个或更多寄存器一起使用时，也会发生这种情况."
"CPU read burst access equal to or more than 9 registers to FMC returns corrupted data starting from the 9th read word. These bursts can only be generated by Cortex®-M4 CPU and not by the other masters (i.e not by DMA). This issue occurs when the stack is remapped on the external memory on the FMC and POP operations are performed with 9 or more registers. This also occurs when LDM/VLDM operations are used with 9 or more registers."
这篇关于LDMIA 指令在 Cortex M4 中的外部 SRAM 上无法正常工作的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
