是否可以在运行时在 M0+ 上设置 ISR 处理程序 [英] Is it possible to set ISR Handler at runtime on M0+

问题描述

我的 SAMD21 ARM M0+ 有一个默认"resetVectors.c 文件.它看起来像:

I have a "default" resetVectors.c file for my SAMD21 ARM M0+. It has something that looks like:

__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
    ...
};

其中定义了不同处理程序存根的位置.出于测试目的，我想使用其中一个未使用的外设 IRQ.

in it that defines where different handler stubs. For testing purposes, I want to use one of the unused peripheral IRQs.

默认情况下，未使用的地址设置为 NULL 地址.我已经向自己证明我可以修改该文件并在编译时更改我未使用的 IRQ (21) 以触发处理程序.但是，是否可以在编译时间之外执行此操作?

By default, the unused ones are set to NULL addresses. I have demonstrated to myself that I can modify that file and at compile time change my unused IRQ (21) to fire a handler. BUT, is it possible to do this outside of compile time?

我观察到该表似乎基于偏移量 0.所以我尝试了这个:

I observed that the table appears to be based at offset 0. So I tried this:

DeviceVectors *table = 0x0000000;
table->pvReserved21 = PV21Handler;

但这只是挂起董事会.有没有动态的方式在运行时分配处理程序?

But that just hangs the board. Is there a dynamic way to assign the handler at runtime?

推荐答案

在 Cortex-M 中，可以在运行时设置向量表的地址.因此，为了设置特定的向量，您需要将向量表定位到 RAM 中.

In Cortex-M it is possible to set the address of the vector table at runtime. So in order to set a specific vector, you need to locate the vector table into RAM.

这种情况下最简单的方法是将exception_table指向的向量表复制到RAM中，在RAM复制中修改需要改变的具体向量，然后将向量表切换到RAM复制.

The simplest method in this case is to copy the vector table pointed to by exception_table to RAM, modify the specific vector you need to change in the RAM copy, then switch the vector table to the RAM copy.

但是请注意，矢量表偏移寄存器 在 Cortex-M0+ 上是可选的，可能并非在所有设备上都实现.然而，它是在 SAMD21 上实现的(参见 数据表摘要<的 7.1.1/a>.

Note however that the Vector Table Offset Register is optional on Cortex-M0+ and may not be implemented on all devices. It is however implemented on SAMD21 (see 7.1.1 of the datasheet summary.

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