虚拟索引物理标记缓存同义词 [英] Virtually indexed physically tagged cache Synonym

问题描述

我无法完全理解 VIPT 缓存中的同义词或别名的概念.

I am not able to entirely grasp the concept of synonyms or aliasing in VIPT caches.

考虑将地址拆分为:-

这里，假设我们有 2 个页面，其中不同的 VA 映射到相同的物理地址(或帧号).

Here, suppose we have 2 pages with different VA's mapped to same physical address(or frame no).

VA 的 pageno 部分(位 13-39)被转换为 PA 的 PFN(位 12-35)并且两者的 PFN 保持相同VA 映射到相同的物理帧.

The pageno part of VA (bits 13-39) which are different gets translated to PFN of PA(bits 12-35) and the PFN remains same for both the VA's as they are mapped to same physical frame.

现在两个 VA 的 pageoffset 部分(位 0-13)与它们想要从特定帧访问的数据相同.

Now the pageoffset part(bits 0-13) of both the VA's are same as the data which they want to access from a particular frame no is same.

由于两个 VA 的 pageoffset 部分相同，位 (5-13) 也将相同，因此 索引或设置号是相同的，因此有应该无混叠，因为只有单个集合或索引号被映射到物理帧号.

As the pageoffset part of both VA's are same, bits (5-13) will also be same, so the index or set no is the same and hence there should be no aliasing as only single set or index no is mapped to a physical frame no.

如图所示的第 12 位如何负责混叠?我无法理解.

How is bit 12 as shown in the diagram, responsible for aliasing ? I am not able to understand that.

如果有人能在地址的帮助下举个例子就好了.

It would be great if someone could give an example with the help of addresses.

谢谢.

推荐答案

页面偏移量是位 0-11，而不是 0-13.看看你的底部图表:页面偏移量是低 12 位，所以你有 4k 个页面(如 x86 和其他常见架构).

The page offset is bits 0-11, not 0-13. Look at your bottom diagram: the page offset is the low 12 bits, so you have 4k pages (like x86 and other common architectures).

如果任何索引位来自页面偏移上方，VIPT 不再 表现得像一个 PIPT，索引位可以自由转换.这里就是这种情况.

If any of the index bits come from above the page offset, VIPT no longer behaves like a PIPT with free translation for the index bits. That's the case here.

一个进程可以将相同的物理页面(框架)映射到 2 个不同的虚拟页面.

A process can have the same physical page (frame) mapped to 2 different virtual pages.

您声称​​不同的 VA 的 pageno 部分(第 13-39 位)被转换为 PA(第 12-35 位)的 PFN，并且两个 VA 的 PFN 保持相同虚假.翻译可以改变位#12.所以其中一个索引位确实是虚拟的而不是物理的，因此同一物理行的两个条目可以放在不同的集合中.

Your claim that The pageno part of VA (bits 13-39) which are different gets translated to PFN of PA(bits 12-35) and the PFN remains same for both the VA's is totally bogus. Translation can change bit #12. So one of the index bits really is virtual and not also physical, so two entries for the same physical line can go in different sets.

我认为我的主要困惑在于页面偏移范围.PA 和 VA 是否相同(即 0-11)，还是 VA 为 0-12，PA 为 0-11?他们会永远一样吗?

I think my main confusion is regarding the page offset range. Is it the same for both PA and VA (that is 0-11) or is it 0-12 for VA and 0-11 for PA? Will they always be same?

PA 和 VA 总是一样的.页偏移量未标记在图表的 VA 部分，仅标记用作索引的位范围.

It's always the same for PA and VA. The page offset isn't marked on the VA part of your diagram, only the range of bits used as the index.

它没有任何不同是没有意义的:虚拟和物理内存都是字节可寻址(或字可寻址).当然，页框(物理页)与虚拟页的大小相同.在从虚拟到物理的转换过程中向右或向左移动地址是没有意义的.

It wouldn't make sense for it to be any different: virtual and physical memory are both byte-addressable (or word-addressable). And of course a page frame (physical page) is the same size as a virtual page. Right or left shifting an address during translation from virtual to physical would make no sense.

正如评论中所讨论的:

我最终找到了http://www.cse.unsw.edu.au/~cs9242/02/lectures/03-cache/node8.html(包括问题中的图表！).它说的是同样的事情:物理标记确实解决了缓存同音问题，作为上下文切换刷新的替代方法.

I did eventually find http://www.cse.unsw.edu.au/~cs9242/02/lectures/03-cache/node8.html (which includes the diagram in the question!). It says the same thing: physical tagging does solve the cache homonym problem as an alternative to flushing on context switch.

但不是同义词问题.为此，您可以让操作系统确保每个 VA 的第 12 位 = 每个 PA 的第 12 位.这称为页面着色.

But not the synonym problem. For that, you can have the OS ensure that bit 12 of every VA = bit 12 of every PA. This is called page coloring.

页面着色还可以解决同音异义问题，而无需硬件重叠标记位，因为它提供了 1 个物理地址和虚拟地址之间相同的位.物理 idx = 虚拟 idx.(但是如果硬件想要依赖这个不变量，那么它就会依赖于软件是正确的.)

Page coloring would also solve the homonym problem without the hardware doing overlapping tag bits, because it gives 1 more bit that's the same between physical and virtual address. phys idx = virt idx. (But then the HW would be relying on software to be correct, if it wanted to depend on this invariant.)

标签与索引重叠的另一个原因是驱逐期间的回写:

外层缓存几乎都是PIPT，而内存本身显然需要物理地址.因此，当您将其发送到内存层次结构时，您需要一行的物理地址.

Outer caches are almost always PIPT, and memory itself obviously needs the physical address. So you need the physical address of a line when you send it out the memory hierarchy.

写回缓存需要能够在对存储的 TLB 检查完成很久之后驱逐脏行(将它们发送到 L2 或物理 RAM).与加载不同的是，除非您将其存储在某个地方，否则您不会仍然有 TLB 结果浮动.VIPT 怎么样L1->L2 驱逐的 PIPT 转换工作

A write-back cache needs to be able to evict dirty lines (send them to L2 or to physical RAM) long after the TLB check for the store was done. Unlike a load, you don't still have the TLB result floating around unless you stored it somewhere. How does the VIPT to PIPT conversion work on L1->L2 eviction

让标签包含页面偏移量上方的所有物理地址位解决了这个问题:给定页面偏移量索引位和标签，您可以构建完整的物理地址.

Having the tag include all the physical address bits above the page offset solves this problem: given the page-offset index bits and the tag, you can construct the full physical address.

(另一种解决方案是直写缓存，因此您确实总是拥有来自 TLB 的物理地址与数据一起发送，即使它不能从缓存标签 + 索引重建.或者对于只读缓存，例如指令缓存，没有回写；驱逐 = 丢弃.)

(Another solution would be a write-through cache, so you do always have the physical address from the TLB to send with the data, even if it's not reconstructable from the cache tag+index. Or for read-only caches, e.g. instruction caches, there is no write-back; eviction = drop.)

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