与缓存预取提示相反 [英] Opposite of cache prefetch hint

问题描述

是否可以在我的代码中添加一个提示，指示应该从缓存中删除一行?与预取提示相反，这表明我很快就会需要一行.就我而言，我知道什么时候我暂时不需要线路，所以我希望能够摆脱它，为我确实需要的线路腾出空间.

解决方案

出于信息目的(假设您在特权上下文中运行)，您还可以使用 invd(作为从轨道核弹的选项).这:

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使处理器的内部缓存无效(刷新)并发出一个特殊功能的总线周期缓存也刷新自己.保存在内部缓存中的数据不会写回主内存.

或 wbinvd，其中:

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将处理器内部缓存中所有修改过的缓存行写回主内存，并使缓存行无效(刷新)内部缓存.然后该指令发出一个特殊功能的总线周期，指示外部缓存也写入返回修改后的数据和另一个总线周期以指示外部缓存应该无效.

未来可以将其纳入 ISA 的指令是 club.尽管这不符合您的需要(因为它不一定会使该行无效)，但为了完整性还是值得一提的.这将:

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将包含内存指定的线性地址的缓存行(如果是脏的)写回内存来自缓存一致性域中缓存层次结构的任何级别的操作数.该行可能保留在处于未修改状态的缓存层次结构.保留缓存层次结构中的行是一种性能优化(被硬件视为提示)以减少后续访问中缓存未命中的可能性.硬件可能选择在缓存层次结构中的任何级别保留该行，并且在某些情况下，可能会使该行无效从缓存层次结构.

Is there a hint I can put in my code indicating that a line should be removed from cache? As opposed to a prefetch hint, which would indicate I will soon need a line. In my case, I know when I won't need a line for a while, so I want to be able to get rid of it to free up space for lines I do need.

解决方案

clflush, clflushopt

Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the linear address specified with the memory operand. If that cache line contains modified data at any level of the cache hierarchy, that data is written back to memory.

They are not available on every CPU (in particular, clflushopt is only available on the 6th generation and later). To be certain, you should use CPUID to verify their availability:

The availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH (CPUID.01H:EDX[bit 19]).

The availability of CLFLUSHOPT is indicated by the presence of the CPUID feature flag CLFLUSHOPT (CPUID.(EAX=7,ECX=0):EBX[bit 23]).

If available, you should use clflushopt. It outperforms clflush when flushing buffers larger than 4KiB (64 lines).

This is the benchmark from

For informational purpose (assuming you are running in a privileged context), you can also use invd (as a nuke-from-orbit option). This:

Invalidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.

or wbinvd, which:

Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write back modified data and another bus cycle to indicate that the external caches should be invalidated.

A future instruction that could make it into the ISA is club. Although this won't fit your need (because it doesn't necessarily invalidate the line), it's worth mentioning for completeness. This would:

Writes back to memory the cache line (if dirty) that contains the linear address specified with the memory operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization (treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from the cache hierarchy.

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