布尔逻辑与放大器;门延迟 [英] Boolean Logic & gate delays

问题描述

假设2门延迟一笔或随身携带的功能，估计波传送进位加法的加法器具有以下字长时间： -

Assuming 2 gate-delays for a Sum or Carry function, estimate the time for ripple-through carry addition for adders with the following word lengths:-

i) 4-bit
ii) 8-bit
iii) 16-bit

在我的笔记我已经写：
延迟是字宽次，每次位级的延迟（2门延迟）。因此：

In my notes I have written: "delay is the word width times each bit stage delay (2 gate delays)". Therefore:

i) 2*4 = 8
ii) 2*8 = 16 
iii) 2*16 = 32

看着脉动进位加法器维基百科页面：
http://en.wikipedia.org/wiki/Ripple_carry_adder#Ripple-carry_adder

这里使用的公式是不同的，任何人都可以解释我的笔记和维基百科文章之间的差异。其中两个是正确的？

The formula used here is different, can anyone explain the discrepancy between my notes and the wikipedia article. Which of the two is correct?

请多多关照。

乔

推荐答案

你可以从链接的维基百科文章在图中看到，你的假设是一种简化：

As you can see from the figure in the linked wikipedia article, your assumption is a simplification:

有关C_out关键路径中包含的三门，即延迟。然而，需要只为第一级三个延迟，由于用于以下仅C_IN的变化，什么导致只有两个门用于第二和所有以下阶段的关键路径。

The critical path for C_out contains three gates, i.e. delays. However, you need the three delays only for the first stage, since for the following only C_in changes, what leads to a critical path of only two gates for the second and all following stages.

这篇关于布尔逻辑与放大器;门延迟的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！